Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

Dynamic Random-Access Memory (DRAM), as the core component of storage systems, offers a simple structure, high storage density, low unit cost, and fast read and write speeds. It is a key support for smart Internet of Things (IoT) devices to achieve low power consumption and high-density upgrades. Low-power, high-density DRAM technology has become a current research hotspot in the field of storage. In sense amplifiers, research focuses on offset compensation, noise immunity, and pre-sensing technology to improve accuracy under low-voltage operation and reduce power consumption. Using advanced Complementary Metal-Oxide-Semiconductor (CMOS) processes can reduce leakage current, lower operating voltage, and enhance process compatibility for high-density integration. 3D stacking technology breaks the physical limitations of planar DRAM through vertical integration that improves DRAM density and data retention capability. Starting from the above three major modules, this paper systematically reviews representative research achievements in low-power, high-density DRAM over the past few years. It analyzes the innovation paths and performance optimization effects of each module, and summarizes the development trends of low-power DRAM technology.

This paper proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-Monte Carlo (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a 3-Stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65 nm process demonstrated that the proposed 3-Stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the Standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian Optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield, and is expected to contribute to next-generation memory circuit design automation.

Sense amplifiers have of late become an important class of circuits due the major role they play in the design of low voltage memory design. It is an active circuit capable to enhance signal promulgation from the selected cell in a memory array to peripheral logic circuits and changes the random logic levels on a bit-line to the digital logic levels of the Boolean circuits in the periphery. In this paper the memristor loaded cross-coupled differential voltage sense amplifier is proposed as a possible surrogate for CMOS based cross coupled differential amplifier to reduce the area size, increase the gain and the speed of operation. With the exponential increase in the memory array sizes the bit line capacitance and cell-access resistance has become very large and this merger conjoined with the further reduction in output energy produced by the cell during reading will aggregate in the generation of a small signals from each selected cell. These small signals will make it difficult for data value detection and determination and will cause a prolonged latency times. To enhance performance speed and to provide signals that can be properly read as logic 0/1 many sense amplifiers have been designed to give faster sensing by responding to low voltage swings. To improve the gain of the sense amplifier by increasing the load resistance the memristor cells is in cooperated in amplifier. The memristor was selected as it propound reduced leakage current, populate less space area and because of quantization of conductance using memristive state allows for easy adjustability of the sense amplifier. The proposed memristor loaded sense amplifier was compared to the conventional CMOS based cross-coupled sense amplifier.

Sense amplifiers play an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read operations. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. A sense amplifier compares the bit line voltage and its complement, and then amplifies it to rail to rail output voltages. In this project, several latch type sense amplifier have been designed and simulated using 90nm CMOS technology with a supply voltage of 1.2V. Sensing delay is one of the important factors in sense amplifier design and it will be calculated for all sense amplifiers by performing voltage scaling.

This paper investigates the viability and compares the merits of small-signal differential sensing and large-signal single-ended sensing scheme for FinFET SRAM under fin Line-Edge-Roughness (fin LER) and Work-Function-Variation (WFV). The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected Bit-Line (BL), and variation of sense amplifier offset voltage (for differential sensing) and trip voltage (for large-signal sensing) are considered simultaneously at subthreshold (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> =0.4V) and superthreshold (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> =1.0V) regions. For differential sensing, the subthreshold sensing margin is severely degraded by the variation in Bitline voltage and sufficient time before enabling the sense amplifier is required to improve the limited margin. For large-signal sensing scheme, we show that there is large disparity between the sense "0" margin and sense "1" margin with the significantly worse sense "0" margin limiting the affordable number of cells per Bitline. The possibility of using double-fin PFET in large-signal sensing inverter to improve the sense "0" margin is examined, and shown to be of limited benefit, especially for operation in subthreshold region. Compared with BULK CMOS, the superior electrostatic integrity and variability of FinFET enhances/enables the feasibility of differential sensing in subthreshold/superthreshold SRAM applications.

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.

This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to 10 THz. The paper also presents a physical design and interfacing logic for interfacing CMOS Memory arrays to Sense amplifiers and related control circuits.

In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance~25.3M, low input impedance~44, wide bandwidth~498 MHz, low input voltage ~ 415 mV, low output voltage ~ 149 mV and low current transfer error ~1.3% (all at 10 ¿A) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35 ¿m CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

Increased process variation and reduced operating voltage present two of the main challenges in using sense amplifiers for small geometry bulk CMOS process technology. This fact coupled with the need to increase on-chip memory to reduce traffic on the bus and increase performance creates the need for a robust and reliable sense amplifier - a differentiating factor in memory area, power, and speed. We present a detailed study of the Voltage Latched Sense Amplifier (VLSA) and the Current Latched Sense Amplifier (CLSA) design in 28nm industry standard process technology [1][2]. We present results on how the two sense amplifier behave for the two design topology for low power (LP) process technology optimized for mobile low leakage application and the second one is high performance High Performance (HP) applications. Detailed Spice simulation with statistical models and Monte Carlo simulations is utilized to compare the two designs for active power, leakage power, speed, and area. Our study shows that VLSA performs better than CLSA - being 67% faster, 35% smaller area, and similar active power for the LP. The VLSA also performed better than the CLSA is the HP technology as well. The sensitivity to temperature for the LP technology node was more at high voltage but for the HP process the lower voltage perform worse.

This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (VOS) of current latch SA calculated solely from threshold voltage (VT) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense “0” hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications.