Realization of an FPGA-based Motion control system for electric standing wheelchairs

As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can't be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA's speed. After testing, this method can effectively meet the requirement of real-time data processing.

Pulse Width Modulation (PWM) is a very common technique used in many different applications. The Conventional method its generation is the heart of the inverter system. This paper present methodology to generate Sinusoidal PWM (SPWM) signal for three-phase inverter based on EP20K200EFC484-2x Altera Field Programmable Gate Array (FPGA). Designing a PWM inverter drive using FPGA has several advantages, such as: it's quick, very modifiable, and very suitable for prototyping. In this paper, the PWM signal is used control switching action conducted by MOSFET as part of power electronics devices in resonant power converter which has 24 volt DC input voltage. As the result, by using resonant oscillation controlled by FPGA the high sinusoidal voltage until 1.0 kV peak-to peak has been generated in the load side. DOI: http://dx.doi.org/10.11591/ijpeds.v3i3.4316

A Brain-Computer-Interface (BCI) based system with a System on a Programmable Chip (SOPC) platform by using of the Steady-State Visually Evoked Potentials (SSVEP) through a Bluetooth interface was proposed in this paper. The proposed BCI system can aid the Amyotrophic Lateral Sclerosis (ALS) or other paralyzed patients to easily control an electric wheelchair in their live. The electroencephalogram (EEG) signals may be detected by electrodes and extracting chip when the patients gazed a flickered target with a specific frequencies. Then these signals can be transformed by FFT into frequency domain and then transmitted to the hardware of electric wheelchair by using of Bluetooth interface. Finally, the electric wheelchair can be moved smoothly in accordance with commands converted by the frequencies of the EEG signal. The experimental results had shown that the proposed system can easily control electric wheelchairs.

This paper proposes a development of Pulse-Width Modulation (PWM) switching signals based on Field Programmable Logic Array (FPGA) and Digital Signal Processor (DSP) to control multi-input interleaved DC/DC converter (MIC). The proposed PWM signals for the MIC do not only require a control of duty cycle, but also operation at different PWM frequency. In order to solve this problem, a simple programmable control scheme using a digital controller can be employed to facilitate the realization of PWM signals generation. The PWM signals are designed by using Altera Cyclone II FPGA board. The duty cycle employed to regulate output voltage is attained from the dSPACE DS1103 board using a Proportional-Integral (PI) controller. This paper also highlights design guidelines, simulation and experimental results. Experiment results show that the proposed DC converter can be driven by PWM signals, by integration of both controllers.

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

As well-known, system on a programmable chip (SOPC) is widely used in a variety of field control systems , due to their flexible configurations and intelligent stand-alone characteristics. They are also increasingly used in astronomical instrument control nowadays. For those complex and diverse systems, a number of different control strategies are stored in FLASH, but the controller of on-chip determines which one to load. At the same time, it can be switched intelligently and remotely to form a multi-strategy control system, so as to extend the control functions and achieve system on-line reconfiguration quickly. In this paper we describe a design concept and realization method of a multistrategy control system on the basis of FPGA-based system on a chip. Its hardware core is Altera's Cyclone series EP3C25 chip .In SOPC BUILDER development environment ,a control system is constructed, which consists of NIOS II soft core as CPU ,REMOTE_UPDATE IP core and control algorithms as well. The concept and design has been verified in the field controllers for various astronomical applications. Satisfactory results have been obtained.

The main objective of this work is to improve the performance of Multilevel Inverter by using the novel LS-PD- PWM and controlling technique instead of the existing approach. The proposed work focus on closed loop controller such as existing PI and Fuzzy Logic Controller for resistive load with Multilevel Inverter. The proposed Asymmetric fifteen level Inverter offers less THD and high frequency than the Asymmetric nine level inverter. Asymmetric multilevel inverter is used to reduce the switching losses and THD. In this work is the generation and implementation of Pulse Width Modulation (PWM) techniques using Field Programmable Gate Array (FPGA) for Multilevel Inverter. PWM can be generated via Microprocessors, Microcontroller, FPGA and DSP Processors. Higher density Programmable Logic Devices (PLD) such as FPGAs can be used to amalgamate large amounts of logic into a single Integrated. Pulse width modulation (PWM) is generally used in power converter control. To generate LS-PD- PWM by using FPGA, this occupies less memory capacity and accurate than conventional one. An efficient PWM generation technique is performed using FPGA for lower frequency applications. Simulation and synthesis is done by ModelSim6.3c and Xilinx10.1. Further, the Implementation is carried out by FPGA Spartan3 Xc3s50. Key Word: PWM, FPGA, PLD (Programmable Logic Devices), LS-PD-PWM

The new generation of field programmable gate array(FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip(SOPC) developing environment. Therefore, this study presents a speed control integrated circuit(IC) for stepping motor drive under this SOPC environment. The design, using FPGA of Spartan-3E series, has realized a subdivision-variation control system for stepping motor. The bottom-top design method is applied in this study. The scheme integrates the current-feedback SPWM principle, the PI regulating technique, the closed-loop control and EDA design technology. The problem of high-subdivision stepping angle is solved effectively. Experimental results indicate that the control system can improve the control precision of stepping motor and make it run more smoothly.

A novel pulse width modulation (PWM) signal generation technique is proposed. The generator converts a single-bit digital signal into a PWM signal without a ramping waveform generator. The proposed PWM signal generators are based on the concept of Delta-Sigma (/spl Delta//spl Sigma/) modulation. A comparator with hysteresis is used instead of a quantizer in the /spl Delta//spl Sigma/ modulator. The switching frequency of the PWM signal decreased with increase of the hysteresis width. The noise-shaped output is obtained and a high signal to noise ratio (SNR) is achieved. In this paper, a 1st-order PWM signal generator is presented. In order to obtain a much higher precision PWM signal a 2nd-order PWM signal generator is discussed. But the 2nd-order PWM is unstable. Hence, PI compensation is applied to stabilize the modulator. A better PWM signal generator with PI compensation is presented. From the improved generator, a low distortion PWM signal was generated, and the SNR of output signal is increased about 20 dB compared to the 1st-order PWM signal generator.

A stepper motor subdivided control system based on SOPC (system on a programmable chip) technology is designed in this paper. Using the TFG (task flow graph) model, the system is designed to satisfy the requirement of some micromanipulation. The design method is based on the TFG model of the digital signal process algorithm and implemented with SOPC technology. As is known, stepper motor system consists of three parts which are control section, driver section and stepper motor. Under the analysis of the stepper motor subdivided principle which gives its precise control method, the architecture of the system and the practical driver circuit as the control circuit are provided. The Nios II CPU is selected for the SOPC system as the control core. The software flow process chart of the subdivided control according to the timing requirement of LMD18245 which is the driver chip for the stepper motor is also offered. In the end, the picture of the substance of the system is shown.

Universal motors are widely used in various applications due to their versatility in operating with both AC and DC power sources. However, controlling the speed of these motors efficiently while maintaining the desired performance characteristics presents a significant challenge. This paper proposes a novel approach for universal motor speed control leveraging the Pulse Width Modulation (PWM) technique. The proposed method utilizes PWM signals to control the average voltage supplied to the motor, thereby regulating its speed. By adjusting the duty cycle of the PWM signal, the effective voltage across the motor can be modulated, enabling precise speed control across a wide range of operating conditions. This paper discusses the theoretical background of PWM and its application in motor speed control. It elaborates on the design considerations and implementation details necessary for integrating PWM-based speed control into universal motor systems. Furthermore, the advantages of PWM-based control, such as improved efficiency, reduced noise, and enhanced dynamic response, are explored. Experimental results demonstrate the effectiveness of the proposed PWMbased speed control technique in regulating the speed of universal motors under various load conditions. The system exhibits robust performance, achieving accurate speed control with minimal power losses. In conclusion, the proposed PWM-based speed control technique offers a versatile and efficient solution for regulating the speed of universal motors, enhancing their applicability in a wide range of industrial and consumer applications.

Non-linear solar photovoltaic (SPV) system characteristics and its dependency on meteorological variables of irradiance and temperature; renders this energy source rather involved to visualize. In this paper a low power realtime SPV module simulator is realized in field programmable gate array (FPGA) XCS100E platform for classroom teaching. FPGA platform is used due to its parallel computing nature and lucid hardware description languages (HDL) available. Output of FPGA being high frequency PWM (pulse width modulated) signals, can be used to upgrade the realized simulator at actual power levels through power electronics interfacing. SPV module with MPPT enabling feature is included, which can be used for testing and deployment of various MPPT techniques.

A sine generation method that the different frequent sine signals can be generated by the different Pulse-Width Modulation (PWM) signals generated by Field-Programmable Gate Array (FPGA) through low-pass filter of fixed parameters was proposed. The method just takes a few FPGA resources and was proved feasible by the theory. The experiment results and theory analysis tally.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

A highly functional circuit for pulse width modulation (PWM) signal processing is proposed as a core of the A-D merged circuit architecture for time-domain information processing. The core circuit employs a switched-current integration technique as its computing architecture and functions as a linear arithmetic operator, a memory, and also a delaying device of PWM signals. A 0.8-/spl mu/m CMOS test chip includes 110 transistors plus two capacitors and performs parallel additions and multiplications at the accuracy of 1.2 ns. A cumulative property of the technique allows the circuit to serve as a low-power accumulator that consumes 23% of the energy of the full digital 7-b accumulator. A PWM multiply-accumulate unit and a nonlinear operation unit are also proposed to extend functionality of the circuit. Since the PWM signal carries multibit data in a binary amplitude pulse, these circuits can be favorably applicable to low-voltage and low-power designs in the deep submicrometer era.