A multistrategy control system for field controllers of astronomical instruments

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

With the characteristics of convenience and mobility, electric standing wheelchairs (ESW) enable patients to freely move and stand up. Being extensively utilized, electric wheelchairs have already been one of the indispensable medical rehabilitation devices. Without doubt, the increase of standing function on electric wheelchairs would be further beneficial to patients. The controller system of the ESW is mainly based on the SoPC (System on a Programmable Chip) constructed by FPGA (Field Programmable Gate Array) and one Nios II processor produced by Altera company. The electric wheels are built up by two DC rim motors while the standing frame is composed of a linear motion mechanism and a parallel four-bar linkage mechanism. The motion controller IC is realized by PDL with the function of standing frame and two DC rim motors' speed control. The controller of standing frame consists of one motor drive and four channels of PWM (Pulse Width Modulation) signal outputs. Therefore, the necessary all digital drive controller of ESW is realized in one FPGA. This ESW enable not only the two-wheel machine to locate, synchronize, turn left or right, move forward or backward, brake and stop, but also the standing frame to lift and fall. Finally, this work completes one experiment system including a FPGA board, three converters, one two-wheel drive standing wheelchair platform that further evidences both the effectiveness and accuracy of the FPGA-based motion controller for ESW.

A stepper motor subdivided control system based on SOPC (system on a programmable chip) technology is designed in this paper. Using the TFG (task flow graph) model, the system is designed to satisfy the requirement of some micromanipulation. The design method is based on the TFG model of the digital signal process algorithm and implemented with SOPC technology. As is known, stepper motor system consists of three parts which are control section, driver section and stepper motor. Under the analysis of the stepper motor subdivided principle which gives its precise control method, the architecture of the system and the practical driver circuit as the control circuit are provided. The Nios II CPU is selected for the SOPC system as the control core. The software flow process chart of the subdivided control according to the timing requirement of LMD18245 which is the driver chip for the stepper motor is also offered. In the end, the picture of the substance of the system is shown.

As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can't be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA's speed. After testing, this method can effectively meet the requirement of real-time data processing.

This paper introduced an approach to design and implement an embedded SoPC (System on a Programmable Chip) technique with Altera Nios II processor for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software to reduce memory utilization. This is achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as speech signal feature extraction (observation vector). Using Gaussian Mixture Model (GMM) to model the observation vector of voice information. Finally, this model passed to the Hidden Markov Model (HMM) as probabilistic model to process the GMM statistically to make decision on utterance words recognition, whether a single or composite, one or more syllable words (i.e. one, six, target). The total framework was implemented on Altera Cyclone II EP2C70F896C6N FPGA chip sitting on ALTERA DE2-70 Development Board. The utility software which are used as tools for design and development hardware/software are Quartus II 11.0sp1 (32-Bit) and Nios II 11.0spl IDE/C++ respectively. Each word model (template) stored as Transition Matrix, Diagonal Covariance Matrices, and Mean Vectors in the system memory. Each word model utilizes only 4.45Kbytes regardless of the spoken word length. Accuracy of the recognition words (digit/0 to digit/10) given 100% for the individual speaker. Training and recognition software has size (code + initialized data) equal to 312Kbytes.

In order to acquire dorsal hand vein image with good quality and extract vein feature accurately, a near infrared vein image acquisition system based on image quality assessment is proposed in the paper. On the aspect of system construction, the system is developed based on system on a programmable chip (SOPC), image sensor MT9V032 and near infrared light filter are selected respectively, and LED light source array and driving circuit are designed. Meanwhile, the core and transmission modules are designed according to system request. On the aspect of image quality assessment, an assessment method based on image two-dimensional entropy is proposed, which is considered as standard in order to control LED arrays' luminous intensity adaptively and achieve self-optimizing control. Experiment shows that through using the proposed system the acquired vein images have better sharpness and more vein information than other acquired vein images under fixed light.

A FPGA implementation for a model‐based state of charge (SOC) estimation is described in this paper. A Thevenin equivalent circuit model is designed for SOC estimation. The extended Kalman filter (EKF) is designed to complete the SOC estimation, and the error is within 1 % . The FPGA is chosen to achieve realtime SOC estimation. A fast matrix method is proposed to improve the calculation speed of the EKF in FPGA because the EKF algorithm requires many matrix operations. In addition, the embedded system based on the FPGA with a system on a programmable chip (SOPC) technique is built using the Qsys platform in Quartus II. Based on the embedded system, an online testing platform is established to monitor the terminal voltage and load current of the experimental battery in real time; experimental results show that the online SOC estimation is successful. The measurement results show that the FPGA embedded scheme of the EKF allows for successful implementation of the SOC estimation with accuracy and speed. The fast matrix method requires 0.00007 s to implement the SOC estimation and is four times faster than the conventional matrix method.

AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs small FPGA resources and the experiments show that the designed AFDX end system works robustly and correctly.

Locomotive condition monitoring and fault diagnosis system is an important component of modern locomotive, it needs a reliable, high-speed communication network to ensure that the system's reliable operation in the complex locomotive environment. The Controller Area Network (CAN) used in the existing distributed locomotive fault detecting and recording system is not suitable for vehicles bus, so the paper brought forward the scheme using the Multifunction Vehicle Bus (MVB). Firstly, it described the alteration of system structure and operating principle key design concepts in detail, next designed the multi-function interface MVB NIC using SOPC (system on a programmable chip) technology, given the realization of hardware and software, ultimately proceeded the network test in the lab, and verified the correctness and feasibility of the design. The improved network has farther transmission distance, higher rates, better reliability and real-time.

A Brain-Computer-Interface (BCI) based system with a System on a Programmable Chip (SOPC) platform by using of the Steady-State Visually Evoked Potentials (SSVEP) through a Bluetooth interface was proposed in this paper. The proposed BCI system can aid the Amyotrophic Lateral Sclerosis (ALS) or other paralyzed patients to easily control an electric wheelchair in their live. The electroencephalogram (EEG) signals may be detected by electrodes and extracting chip when the patients gazed a flickered target with a specific frequencies. Then these signals can be transformed by FFT into frequency domain and then transmitted to the hardware of electric wheelchair by using of Bluetooth interface. Finally, the electric wheelchair can be moved smoothly in accordance with commands converted by the frequencies of the EEG signal. The experimental results had shown that the proposed system can easily control electric wheelchairs.

A system-on-a-programmable-chip (SOPC) using an Altera FPGA (Stratix EP1S10) and a Nios embedded processor to develop drive system for permanent magnet synchronous motor (PMSM) is presented in this paper. In this SOPC, it has two modules to construct a fully digital drive controller. One module performs the function of the speed/position loop control and motion trajectory control of PMSM drives. The other module performs the function of the current loop control for PMSM drives, which includes vector control, SVPWM generation, coordinate transformation, PI controller and the pulse detection of the quadrature encoder. The former is implemented by software using Nios embedded processor due to the need of complicated control algorithm and low sampling frequency control (motion trajectory control & position control: less than 1kHz). The latter is implemented by hardware due to the need of high sampling frequency control (current loop: 16 kHz, PWM circuit: 4/spl sim/8 MHz) but simple computation. To confirm the effectiveness of the proposed SOPC, an experimental system with a PMSM, a FPGA experimental board, an inverter and a rectifier has been set up and some experimental results have been validated with the theoretical ones.

The new generation of field programmable gate array(FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip(SOPC) developing environment. Therefore, this study presents a speed control integrated circuit(IC) for stepping motor drive under this SOPC environment. The design, using FPGA of Spartan-3E series, has realized a subdivision-variation control system for stepping motor. The bottom-top design method is applied in this study. The scheme integrates the current-feedback SPWM principle, the PI regulating technique, the closed-loop control and EDA design technology. The problem of high-subdivision stepping angle is solved effectively. Experimental results indicate that the control system can improve the control precision of stepping motor and make it run more smoothly.

Unlike a traditional topology of a control system with feedback connected plant and controller systems, this paper discusses a new topology that uses an intermediate network system between the plant and controller systems. More specifically, this paper presents modeling frameworks as well as computational procedures for the design of the closed-loop control system when the nodes of the plant, controller, and network systems fail to operate and the communication links fail to transfer information between communicating nodes. It also discusses conditions required for the synthesis of the controller and network systems, and characterizes the maximum number of unavailable nodes and the maximum probability of unavailable communication links. The aim of the presented results is to provide a more practical approach to the design of the new topology. Also, a four-tank process system is used to demonstrate details of the presented modeling frameworks and computational procedures.

PurposeThe purpose of this paper is to present a complete solution for speed sensorless AC drive with voltage source inverter, induction machine, and motor choke. Major problems with adjustable speed drives are underlined and the use of motor choke is justified. An AC drive with motor choke can work only if specific modifications in the control algorithms are done.Design/methodology/approachThe goal of the paper is to present new nonlinear vector control method for induction motor drive. In the control system, the presence of motor choke is taken into account. The choke changes the structure of the predictive controller and state observer. The new concept of integrating the predictive controller with electromagnetic forces observer is presented. The paper presents theoretical description of the system as well the simulation and experimental verification.FindingsThe paper shows that the suggested decoupled AC drive control system is operating better than a system without decoupling. The system with motor choke requires modifications in the current controller and observer system. With omitting the motor choke a speed sensorless drive cannot work properly.Practical implicationsThe solution is oriented for industrial applications because in numerous industrial dives the motor choke is utilized. However, with motor choke many sophisticated control algorithms cannot work properly. The concept presented in the paper solves such practical problems.Originality/valueThe paper presents a completely new decoupled field‐oriented control system with load angle controller, predictive current controller and state observer for AC drive with motor choke.

In this paper, we present a traffic cyber physical system for urban road traffic signal control, which is referred to as UTSC-CPS. With this proposed system, managers and researchers can realize the construction and simulation of various types of traffic scenarios, the rapid development, and optimization of new control strategies and can apply effective control strategies to actual traffic management. The advantages of this new system include the following. Firstly, the fusion architecture of private cloud computing and edge computing is proposed for the first time, which effectively improves the performance of software and hardware of the urban road traffic signal control system and realizes information security perception and protection in cloud and equipment, respectively, within the fusion framework; secondly, using the concept of parallel system, the depth of real-time traffic control subsystem and real-time simulation subsystem is realized. Thirdly, the idea of virtual scene basic engine and strategy agent engine is put forward in the system design, which separates data from control strategy by designing a general control strategy API and helps researchers focus on control algorithm itself without paying attention to detection data and basic data. Finally, considering China, the system designs a general control strategy API to separate data from control strategy. Most of the popular communication protocols between signal controllers and detectors are private protocols. The standard protocol conversion middleware is skillfully designed, which decouples the field equipment from the system software and achieves the universality and reliability of the control strategy. To further demonstrate the advantages of the new system, we have carried out a one-year practical test in Weifang City, Shandong Province, China. The system has been proved in terms of stability, security, scalability, practicability and rapid practice, and verification of the new control strategy. At the same time, it proves the superiority of the simulation subsystem in the performance and simulation scale by comparing the different-scale road networks of Shunyi District in Beijing and Weifang City in Shandong Province. Further tests were conducted using real intersections, and the results were equally valid.