The application of multi-function interface MVB NIC in distributed locomotive fault detecting and recording system

A stepper motor subdivided control system based on SOPC (system on a programmable chip) technology is designed in this paper. Using the TFG (task flow graph) model, the system is designed to satisfy the requirement of some micromanipulation. The design method is based on the TFG model of the digital signal process algorithm and implemented with SOPC technology. As is known, stepper motor system consists of three parts which are control section, driver section and stepper motor. Under the analysis of the stepper motor subdivided principle which gives its precise control method, the architecture of the system and the practical driver circuit as the control circuit are provided. The Nios II CPU is selected for the SOPC system as the control core. The software flow process chart of the subdivided control according to the timing requirement of LMD18245 which is the driver chip for the stepper motor is also offered. In the end, the picture of the substance of the system is shown.

Multifunction Vehicle Bus (MVB) is a critical component in the Train Communication Network (TCN), which is widely used in most of the modern train techniques of the transportation system. How to ensure security of MVB has become an important issue. Traditional testing could not ensure the system correctness. The MVB system modeling and verification are concerned in this paper. Petri Net and model checking methods are used to verify the MVB system. A Hierarchy Colored Petri Net (HCPN) approach is presented to model and simulate the Master Transfer protocol of MVB. Synchronous and asynchronous methods are proposed to describe the entities and communication environment. Automata model of the Master Transfer protocol is designed. Based on our model checking platform M3C, the Master Transfer protocol of the MVB is verified and some system logic critical errors are found. Experimental results show the efficiency of our methods.

Multifunction Vehicle Bus (MVB) is a highly robust real-time field bus for rail vehicles. On MVB, periodic process data and sporadic message data are transmitted in the form of telegrams. The main focus of this paper is the development of heuristic scheduling algorithms for periodic telegrams on MVB. We first propose two heuristics that find the best location of individual telegrams in the MVB schedule based on different criteria. Then, we introduce a new swap operation that allows improving MVB schedules by exchanging the locations of telegrams. A comprehensive evaluation based on a large number of test cases shows that the proposed heuristics are able to find feasible and close-to-optimal MVB schedules with practical computation times. In particular, our heuristics clearly outperform an existing ILP formulation, that cannot find optimal or even feasible schedules in cases with large telegram sets.

Multifunction vehicle bus (MVB) is a standard protocol defined in train communication network criterion, and used for transmitting information among various equipments inside the vehicle. In order to insure compatibility and inter-operability among the MVB equipment, it requires that the data transmitted in the bus need to be collected, and correctness and reliability of data transmission of the MVB network should be analyzed. Base on the characters of periodically broadcasting and master slave frame response. According to IEC61375 standard, this paper proposes a method to implement an analyzer for MVB device protocol. In the method, the transmitted data on the bus are sampled using error-tolerance decode algorithm, and then the compatibility and dependability of data transmission among devices are analyzed via protocol analysis application. The experiment results showed that the analyzer can exactly validate the design of the equipment on the MVB bus.

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

Tools on using concept map for knowledge representation, ontology for domain rule generation and conversion from concept map to ontology are invented over recent years. Some focus on graphical representation, such as concept map, of domain knowledge for better user understanding, while others introduce rules that concept map fails to represent to extend the contents of generated ontology. To combine both advantages, a tool Conceptology is presented. In the context of MVB (Multifunction Vehicle Bus) standard domain, a group of generation rules from enriched concept map to OWL (Web Ontology Language) are presented, and Conceptology offers implementation of proposed rules to support graphical representation of MVB domain knowledge and conversion from concept map to OWL. Two Conceptology application cases from MVB standards are demonstrated.

As well-known, system on a programmable chip (SOPC) is widely used in a variety of field control systems , due to their flexible configurations and intelligent stand-alone characteristics. They are also increasingly used in astronomical instrument control nowadays. For those complex and diverse systems, a number of different control strategies are stored in FLASH, but the controller of on-chip determines which one to load. At the same time, it can be switched intelligently and remotely to form a multi-strategy control system, so as to extend the control functions and achieve system on-line reconfiguration quickly. In this paper we describe a design concept and realization method of a multistrategy control system on the basis of FPGA-based system on a chip. Its hardware core is Altera's Cyclone series EP3C25 chip .In SOPC BUILDER development environment ,a control system is constructed, which consists of NIOS II soft core as CPU ,REMOTE_UPDATE IP core and control algorithms as well. The concept and design has been verified in the field controllers for various astronomical applications. Satisfactory results have been obtained.

As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can't be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA's speed. After testing, this method can effectively meet the requirement of real-time data processing.

The standardization of train communications protocols, train communication network (TCN), has created a need to design new electronic devices which can communicate according to them. Up to date, several solutions have been suggested, but every one needs additional circuits. In this article we present a novel flexible architecture which allows the materialization of slave nodes for multifunction vehicle bus (MVB) in a single chip by using reconfigurable logic. Furthermore, a software for definition of specialized architecture for each type of slave node is proposed. The generic architecture includes two standard onchip busses, which are aimed at interconnecting all the modules as cores attached to them by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. As a result, the electronic platform for the slave device has been generated on a field-programmable gate array, FPGA.

This paper discusses about the implementation of an embedded bus interface between a multifunction vehicle bus (MVB) and Ethernet. The proposed MVB-Ethernet interface consists of the MVB board and the embedded ARM board with an Ethernet port. The embedded ARM board consists of ARM processor, Linux operating system, MVB driver, and application program. After the error information processed by a telegram analysis unit, MCU, etc., is transferred to the ARM board from the MVB board, it is analyzed from the PC based on Windows XP. With the MVB-Ethernet interface, the error can be traced every 1 millisecond.

In order to acquire dorsal hand vein image with good quality and extract vein feature accurately, a near infrared vein image acquisition system based on image quality assessment is proposed in the paper. On the aspect of system construction, the system is developed based on system on a programmable chip (SOPC), image sensor MT9V032 and near infrared light filter are selected respectively, and LED light source array and driving circuit are designed. Meanwhile, the core and transmission modules are designed according to system request. On the aspect of image quality assessment, an assessment method based on image two-dimensional entropy is proposed, which is considered as standard in order to control LED arrays' luminous intensity adaptively and achieve self-optimizing control. Experiment shows that through using the proposed system the acquired vein images have better sharpness and more vein information than other acquired vein images under fixed light.

This paper introduced an approach to design and implement an embedded SoPC (System on a Programmable Chip) technique with Altera Nios II processor for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software to reduce memory utilization. This is achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as speech signal feature extraction (observation vector). Using Gaussian Mixture Model (GMM) to model the observation vector of voice information. Finally, this model passed to the Hidden Markov Model (HMM) as probabilistic model to process the GMM statistically to make decision on utterance words recognition, whether a single or composite, one or more syllable words (i.e. one, six, target). The total framework was implemented on Altera Cyclone II EP2C70F896C6N FPGA chip sitting on ALTERA DE2-70 Development Board. The utility software which are used as tools for design and development hardware/software are Quartus II 11.0sp1 (32-Bit) and Nios II 11.0spl IDE/C++ respectively. Each word model (template) stored as Transition Matrix, Diagonal Covariance Matrices, and Mean Vectors in the system memory. Each word model utilizes only 4.45Kbytes regardless of the spoken word length. Accuracy of the recognition words (digit/0 to digit/10) given 100% for the individual speaker. Training and recognition software has size (code + initialized data) equal to 312Kbytes.

A FPGA implementation for a model‐based state of charge (SOC) estimation is described in this paper. A Thevenin equivalent circuit model is designed for SOC estimation. The extended Kalman filter (EKF) is designed to complete the SOC estimation, and the error is within 1 % . The FPGA is chosen to achieve realtime SOC estimation. A fast matrix method is proposed to improve the calculation speed of the EKF in FPGA because the EKF algorithm requires many matrix operations. In addition, the embedded system based on the FPGA with a system on a programmable chip (SOPC) technique is built using the Qsys platform in Quartus II. Based on the embedded system, an online testing platform is established to monitor the terminal voltage and load current of the experimental battery in real time; experimental results show that the online SOC estimation is successful. The measurement results show that the FPGA embedded scheme of the EKF allows for successful implementation of the SOC estimation with accuracy and speed. The fast matrix method requires 0.00007 s to implement the SOC estimation and is four times faster than the conventional matrix method.

AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs small FPGA resources and the experiments show that the designed AFDX end system works robustly and correctly.

A Brain-Computer-Interface (BCI) based system with a System on a Programmable Chip (SOPC) platform by using of the Steady-State Visually Evoked Potentials (SSVEP) through a Bluetooth interface was proposed in this paper. The proposed BCI system can aid the Amyotrophic Lateral Sclerosis (ALS) or other paralyzed patients to easily control an electric wheelchair in their live. The electroencephalogram (EEG) signals may be detected by electrodes and extracting chip when the patients gazed a flickered target with a specific frequencies. Then these signals can be transformed by FFT into frequency domain and then transmitted to the hardware of electric wheelchair by using of Bluetooth interface. Finally, the electric wheelchair can be moved smoothly in accordance with commands converted by the frequencies of the EEG signal. The experimental results had shown that the proposed system can easily control electric wheelchairs.