Reconfigurable System Design and Verification

We introduce a re-configurable system design for positron emission tomography (PET) for purpose of maximizing the cost effectiveness of PET. In this new design concept, a PET system employs a small number of compact, flat-panel (cFP) PET detectors (which we believe will be made available in near future by us or others) to assume various scanner geometries so that the performance properties desired in various imaging applications can be met by a single PET system. For purpose of demonstration, we consider the design of a re-configurable small-animal system consisting of four cFP detectors that are approximately 8×8 cm2 in size and made of 10mm thick LSO. We consider four geometries for the scanner and conduct Monte-Carlo simulations to study their sensitivity, scatter fractions, random fractions, and noise-equivalent count rates. Our results indicate that, in terms of sensitivity and imaging field-of-view (FOV) the re-configurable system that we consider are very promising for small-animal imaging.

Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere stated in K. Srinivasan and K.S. Chatha (2004)). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60%, ave: 42.02%). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07% and 4.125%, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. This feature enables the substitution of the reconfigurable architecture within a configuration area on the chip. Beneficial here is that the architecture can be adapted to the actual demand of an application while run-time. High performance, flexibility and adaptivity of these devices raise the interest in academic research and also in industrial fields of application. This new method for designing systems isn't supported very well by tools until now. This tutorial should help designers as well as researchers in developing dynamic and partial reconfigurable systems and increase the number of area of applications exploiting this very promising methodology. As an example the design of an on-demand reconfigurable system for inner cabin automotive application will be presented.

A reconfigurable system is a system which may allow the service continuity under failure, on the basis of a reduced level of functionality. In such a system, when one component fails the rest of the system keeps working with some acceptable performance degradation. To distinguish between the normal behavior and the degraded one, the production rate is used as a performance measure. Two optimization problems dealing with reconfigurable systems are addressed. We consider a series system consisting of N stochastically independent components. Different technologies are assumed to be available for each component. The following design problems are studied: (i) Find the configuration which allows maximizing the production rate of the system under resource constraints. (ii) Find the configuration that allows to reach some predetermined level of production rate at minimal cost.

<div class="section abstract"><div class="htmlview paragraph">Modern aerospace industry is continuously seeking new technologies due to potential increase in demand for new aircrafts which are to be produced on a single production line while reducing model changeover time and improving quality of the assembly process. In mass volume production, this can be achieved by fixing a large number of similar components using special-purpose jigs and fixtures. This type of jigs and fixtures can be largely found in Aerospace industry. In low volume production, improvement of re-configurable fixturing systems becomes a favourable way to reduce the cost of production per unit. A re-configurable fixturing system consists of standard components that can be used to satisfy different fixturing requirements. These fixtures are reusable and this enhances their flexibility and reduces the time and cost of development. It also offers the benefit of eliminating the need for dedicated tooling, dedicated fixturing, associated storage and floor space. Re-configurable fixturing also provide rapid response to engineering and production changes, system expandability, and considerable reduction in setup time. In this research a novel concept of re-configurable fixturing system is developed and validated using a fully functional small scale prototype made out of standard parts that are widely available in the market. The developed system can be easily applied to other industries due to its flexibility and re-configurability.</div></div>

BackgroundThird-party electronic health record (EHR) apps allow health care organizations to extend the capabilities and features of their EHR system. Given the widespread utilization of EHRs and the emergence of third-party apps in EHR marketplaces, it has become necessary to conduct a systematic review and analysis of apps in EHR app marketplaces.ObjectiveThe goal of this review is to organize, categorize, and characterize the availability of third-party apps in EHR marketplaces.MethodsTwo informaticists (authors JR and BW) used grounded theory principles to review and categorize EHR apps listed in top EHR vendors’ public-facing marketplaces.ResultsWe categorized a total of 471 EHR apps into a taxonomy consisting of 3 primary categories, 15 secondary categories, and 55 tertiary categories. The three primary categories were administrative (n=203, 43.1%), provider support (n=159, 33.8%), and patient care (n=109, 23.1%). Within administrative apps, we split the apps into four secondary categories: front office (n=77, 37.9%), financial (n=53, 26.1%), office administration (n=49, 24.1%), and office device integration (n=17, 8.4%). Within the provider support primary classification, we split the apps into eight secondary categories: documentation (n=34, 21.3%), records management (n=27, 17.0%), care coordination (n=23, 14.4%), population health (n=18, 11.3%), EHR efficiency (n=16, 10.1%), ordering and prescribing (n=15, 9.4%), medical device integration (n=13, 8.2%), and specialty EHR (n=12, 7.5%). Within the patient care primary classification, we split the apps into three secondary categories: patient engagement (n=50, 45.9%), clinical decision support (n=40, 36.7%), and remote care (n=18, 16.5%). Total app counts varied substantially across EHR vendors. Overall, the distribution of apps across primary categories were relatively similar, with a few exceptions.ConclusionsWe characterized and organized a diverse and rich set of third-party EHR apps. This work provides an important reference for developers, researchers, and EHR customers to more easily search, review, and compare apps in EHR app marketplaces.

Reconfigurable systems are the safe dynamical systems wherein the health of the control input and/or sensor output variables are continuously monitored and then they are reconfigured, if necessary, in an event of an unexpected fault detected online. This idea is applied, in particular, at the reconfigurable system where the number of control variables is more than the state variables considered to define its motion. In this paper, an adaptive pole placing controller is developed for use in such reconfigurable systems. Adaptive pole placing controller, in theory, is adaptive to take a fault size and retain the closed loop poles it assigns at fixed locations in the open left half plane of the complex plane. As a result, when the controller is not adaptive, it means that the pole perturbations could lead to catastrophes. However, to design adaptive pole placing controller for a reconfigurable system, fault size is required. Hence, the primary objective of the paper is to present a simple procedure that determines the fault size for tuning in the adaptive pole placing controller. Both direct and full-order Luenberger observer based state feedback adaptive pole placing controllers are presented. In situations where the adaptive pole placing controller is not possible, the fault size for which the reconfigurable system with a non-adaptive pole placing controller would transit from a stable to unstable system (referred as fault tolerant margin with respect to the non-adaptive pole placing controller) is also presented. Some of these features of this paper are illustrated by using the reconfigurable aircraft model available in the literature.

What is automatized during perceptual categorization?

Reconfiguration for seamless mobility has been identified as a key feature of mobile communications beyond 3G. The reconfigurable system in general comprises users, terminals, various radio access schemes, network operators and service providers. A means is required for capturing key stakeholder attributes and also a method for securely sharing those attributes to allow reconfiguration decisions to be made fairly. Identifying a complete list of beneficiaries and their responsibilities and levels of authority within the reconfigurable system will be a major step forward for resolving various issues arising towards the development of this system including the need for standardization, regulation and overall security architecture. This paper introduces new components within the reconfigurable system aimed at addressing these issues, and proposes a preliminary architecture enabling the exchange of profile data between different networks without compromising their security (privacy, integrity, etc).

This paper discusses about formal verification techniques targeting C based VLSI design descriptions. Recently there are lots of attentions into the use of C programming language (or its extensions) for describing hardware as well as software with an intention to support hardware-software co-design processes with a single language. Here we first discuss about such design methodologies by which system level descriptions for hardware-software combined systems can be uniformly and smoothly refined into implementation in RTL for hardware and assembly languages for software. Starting from regular C programming language descriptions, the design methodologies repeat a number of small refinement steps and gradually adding more and more details into the target designs. We also discuss about formal verification of system level descriptions in those design methodologies from the viewpoint of formal verification. Since such descriptions have essentially concurrency and C must be extended to be able to represent such concurrency, an effective and efficient formal verification of synchronization of concurrent processes is one of the most important issues in system level designs. We present model checking and equivalence checking methods targeting the design methodology that can check correctness of design descriptions with preliminary experimental results. The proposed formal verification methods will support the design methodologies and are very efficient by utilizing the fact that the design methodologies consist of lots of small refinement steps.

FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of hardware functions to be configured typically exceeds the underlying chip area during the execution of an application, previous efforts have introduced configuration caching. Those efforts, however, have focused on two run-time-reconfiguration scenarios, which consider a single application running on the reconfigurable system. In the full reconfiguration scenario, functions of an application are arranged into blocks each of which has enough functions to fill the entire chip. The blocks are configured in a deterministic sequence needed by the application based on the a priori knowledge about the application. In the partial reconfiguration scenario, each function is configured or replaced on a function-by-function basis, based on the application needs. In the former technique, spatial processing locality is well exploited. In the latter, only temporal processing locality is exploited. In this work, we propose a technique suitable for multitasking and for cases of single applications that can change the course of processing in a non-deterministic fashion based on data. In order to exploit processing locality, both spatial and temporal simultaneously, the proposed model groups hardware functions into hardware configuration blocks (pages) of fixed size, where multiple pages can be configured on a chip simultaneously. By grouping only related functions that are typically requested together, processing spatial locality can be exploited. Temporal locality is exploited through page replacement techniques. Data mining techniques were used to group related functions into pages. Standard, replacement algorithms as those found in caching were considered. Simulations, as well as emulation using the Cray XD1 reconfigurable high-performance computer were used in the experimental study. The results show a significant improvement in performance using the proposed paging technique.

In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated on chip accelerators and network interfaces, combined with time to market requirements of the final system necessitated hardware verification and software development on pre-silicon systems that provided a high degree of architecture fidelity, reasonable time to completion for verification tests, and sufficient diagnosis tools for root cause analysis from processor logic to application design. To meet these requirements, we developed an FPGA based emulator which actually implemented the combined chip logic function by mapping it to FPGA equivalent gate functions. This system has the advantage over other simulation environments in that it has actual chip logic that can be executed at real world speeds e.g. MHz, rather than the traditional HDL simulators which are typically executed at 10 or 100's of KHz. Additional flexibility in terms of system verification, analysis and application development was provided by the development of a library OS based programming environment, Bare Metal Application (BMA), complimentary to both the FPGA based system as well as the actual silicon. The main contribution of this work was the development of a reconfigurable and flexible simulation system, both hardware and software which, to the best of our knowledge, provided the first heterogeneous multipurpose environment for silicon and software validation on a system with both general purpose cores and on board accelerators.

Dynamically reconfigurable systems have the potential of realising efficient systems as well as providing adaptability to changing system requirements. Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments. We propose an approach in which reconfiguration is applied dynamically at various levels of a mobile system, whereas traditionally, reconfigurable systems mainly focus at the gate level only. The research performed in the CHAMELEON project 1 aims at designing such a heterogeneous reconfigurable mobile system. The two main motivations for the system are 1) to have an energy-efficient system, while 2) achieving an adequate Quality of Service for applications.

Towards a Reconfigurable Supply Network Model

The flexibility, performance and cost effectiveness of reconfigurable architectures have lead to its widespread use for embedded applications. Coarse-grained reconfigurable system design is very complex for multi-fields experts to collaborate on application algorithm design, hardware/software co-design and system decision. However, existing reconfigurable system design methods and environments can only support hardware/software co-design, ignoring the collaboration between multi-field experts. This paper presents a collaborative partition approach of coarse-grained reconfigurable system design using evolutionary ant colony optimization. We create a distributed collaborative design environment for system decision engineers, software designers, hardware designers and application algorithm developers. The method not only utilizes the advantages of ant colony optimization for searching global optimal solutions, but also provides a framework for multi-field experts to work collaboratively. Experimental results show that the method improves the quality and speed of hardware/software partition for coarse-grained reconfigurable system design.