Redundancy identification and removal based on implicit state enumeration

Automatic definition of macro-actions for Reinforcement Learning (RL) is a way of breaking a large problem into smaller sub-problems. Macro-actions are known to boost the agent's learning process, leading to a better performance. One recent approach, called Laplacian Framework, uses the Proto-Value Functions of the State Transition Graph (STG) associated with a RL problem in order to create options. For larger problems, however, the STG is unavailable. In this context, we propose an improvement upon the Laplacian Framework for large problems, called Laplacian using Abstract State Transition Graphs (LAST-G), which uses an Abstract State Transition Graph (ASTG), a reduced version of the original STG. This approach allows the creation of intra-policies for the discovered options by using the ASTG as a model of the environment. Our experimental results show that the proposed framework is capable of: (i) effectively creating purposeful options; and (ii) successfully executing the identified options.

This brief presents some further results on the finite-time stability of probabilistic logical networks (PLNs). By semi-tensor product technique routinely, the dynamic behavior of a PLN is characterized by its corresponding state transition graph (STG). Then, an irradiative result is found. That is, a PLN is globally stable within finite time, if and only if, its STG is acyclic, except for the self loop at the pre-designated vertex. Based on this observation, some properties of STG, which is associated with a finite-time stable PLN, are formulated. The most significant finding is that the determinant of its anti-adjacency matrix is compactly related to the existence of a Hamilton path and is only equal to 0 or 1. Afterwards, the topological sort of all the vertices in STG is defined. As a consequence, two topological sorting algorithms are presented to analyze the stability of PLNs applicably and efficiently. Finally, a simulation example is employed to illustrate the applicability of the obtained results.

In 1973 R. Thomas introduced a logical approach to modeling and analysis of bioregulatory networks. Given a set of Boolean functions describing the regulatory interactions, a state transition graph is constructed that captures the dynamics of the system. In the late eighties, Snoussi and Thomas extended the original framework by including singular values corresponding to interaction thresholds. They showed that these are needed for a refined understanding of the network dynamics. In this paper, we study systematically singular steady states, which are characteristic of feedback circuits in the interaction graph, and relate them to the type, number and cardinality of attractors in the state transition graph. In particular, we derive sufficient conditions for regulatory networks to exhibit multistationarity or oscillatory behavior, thus giving a partial converse to the well-known Thomas conjectures.

We present a mathematical model of cell fate decision between survival, necrosis and apoptosis as a concrete implementation of the Waddington’s metaphor of epigenetic landscape determining cellular behaviour. We describe the principles of the model construction and in silico experiments performed on it. The genetic network underlying cell fate decisions is reconstructed in the form of an influence diagram together with logical rules defining possible system state changes, while the epigenetic landscape is represented as a state transition graph generated from the discrete cell fate decision model. Stochastic cellular decision making is modeled as a random walk on the state transition graph, assuming equal probabilities of any possible system state update. The probability to reach a particular attractor (stable state) of the state transition graph, starting the random walk from a “physiological” cellular state, is interpreted as a probability of having a particular phenotype (outcome) in a biological experiment. As a result, one can predict the phenotypic probabilities and their changes as a result of specific perturbations. We show that such a “generic” cell model can recapitulate and explain experiments conducted on mice and cell lines and predict the outcome of not yet done experiments. In the discussion, we compare the design principles of the cell fate decision model with the principles of designing engineered devices and underline some important differences.

Manual testing, as a complement to automated GUI testing, is the last line of defense for app quality especially in spotting usability and accessibility issues. However, the repeated actions and easy missing of some functionalities make manual testing time-consuming, labor-extensive and inefficient. Inspired by the game candy crush with flashy candies as hint moves for players, we develop a tool named NaviDroid for navigating human testers via highlighted next operations for more effective and efficient testing. Within NaviDroid, it constructs an enriched state transition graph (STG) with the trigger actions as the edges for two involved states. Based on the STG, NaviDroid utilizes the dynamic programming algorithm to plan the exploration path, and augment the run-time GUI with visualized hint moves for testers to quickly explore untested states and avoid duplication. The automated experiments demonstrate the high coverage and efficient path planning of NaviDroid. A user study further confirms its usefulness in the participants covering more states and activities, detecting more bugs within less time compared with the control group.NaviDroid demo video: https://youtu.be/lShFyg_nTA0.

This paper presents the techniques of implicit traversing and state verification for sequential finite state machines (FSMs) based of on the state collapsing of state transition graph(STG). The problems of state designing are described. In order to achieve high state enumeration coverage, heuristic knowledge is proposed.

This paper considers verification of combinational circuits by test vectors under assumption of gate and wire replacement faults. Identifying redundant faults is critical to the quality and speed of such verification schemes. We propose the first known exact redundancy identification of gate replacement faults, together with its efficient approximations. While both solutions use the SAT formulation of redundancy identification, we propose the means to effectively use any single stuck-at-value redundancy identification in the approximate schemes, with varying detection accuracy. Critical to the latter are the novel uses of don't care approximations that detect many redundant faults and quickly identify those that can be detected by methods for stuck-at value faults. A test generation scheme that uses the error-correcting properties of Arithmetic Transforms is incorporated into the overall verification procedure, and is shown to provide high fault coverage for these fault models.

Sequential testability aspects in the decomposition of finite state machines (FSMs) are addressed. It is shown that the sequential testability of an FSM can be enhanced more easily when the machine is recognized to be, or is synthesized as, an interconnection of smaller machines. An exhaustive classification of redundant faults that can occur in a single FSM embedded in an interacting sequential circuit is presented. Associating each class of these redundant faults with a don't care set, a synthesis procedure is described that exploits the don't cares optimally to obtain an irredundant interacting sequential circuit with no area overhead. The synthesis procedure operates on a distributed-style representation of interacting state transition graphs (STGs), carrying out a series of local analyses. Insights into sequential logic synthesis improving on current optimization techniques for interacting sequential circuits are presented. >

The paper presents an inclusion relation which is used to verify the process of controller synthesis based on incompletely specified finite state machine model. State transition graph is adopted to describe the behavior of controller. State transition graph STG_org was abstract behavior description of controller synthesis generated before synthesized and state transition graph STG_ext was reversely extracted from structure realization of controller synthesis. If STG_org contains STG_ext then corresponding process of controller synthesis was correct. The paper gives a formal verification algorithm of controller synthesis with time complexity. In order to further improve time complexity of algorithm, a verifying algorithm with synthetic information guidance was proposed.

The development of scientific reasoning competencies is a key goal of science education. To better understand the complex construct of scientific reasoning, which includes modeling as one style of reasoning, thorough investigations of the underlying processes are needed. Therefore, in this study, a typology of preservice science teachers’ modeling strategies was developed. Thirty-two preservice science teachers were videotaped while engaging in the modeling task of investigating a black box. Following a qualitative content analysis, sequences of modeling activities were identified. By transforming these sequences of modeling activities into state transition graphs, six types of modeling strategies were derived, differing in the homogeneity and complexity of their modeling processes. The preservice science teachers engaged in activities of (1) exploration only; (2a) exploration and development with a focus on development; (2b) exploration and development with a focus on exploration; (2c) exploration and development, balanced; (3a) exploration, development, and drawing predictions from a model once; or (3b) exploration, development, and repeatedly drawing predictions from a model. Finally, this typology is discussed regarding the process of its development and its potential to inform and guide further research as well as the development of interventions aiming to foster competencies in scientific modeling.

An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at-fault model; for PLAs, an extended fault model called the crosspoint fault model has been used. The authors propose a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented which show that the area/performance penalties in return for easy testability are small.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A formalism based on piecewise-linear (PL) differential equations, originally due to Glass and Kauffman, has been shown to be well-suited to modelling genetic regulatory networks. However, the discontinuous vector field inherent in the PL models raises some mathematical problems in defining solutions on the surfaces of discontinuity. To overcome these difficulties we use the approach of Filippov, which extends the vector field to a differential inclusion. We study the stability of equilibria (called singular equilibrium sets) that lie on the surfaces of discontinuity. We prove several theorems that characterize the stability of these singular equilibria directly from the state transition graph, which is a qualitative representation of the dynamics of the system. We also formulate a stronger conjecture on the stability of these singular equilibrium sets.

Today statecharts are a de facto standard in industry for modeling system behavior. Test data generation is one of the key issues in software testing. This paper proposes an reduction approach to test data generation for the state-based software testing. In this paper, first state transition graph is derived from state chart diagram. Then, all the required information are extracted from the state chart diagram. Then, test cases are generated. Lastly, a set of test cases are minimized by calculating the node coverage for each test case. It is also determined that which test cases are covered by other test cases. The advantage of our test generation technique is that it optimizes test coverage by minimizing time and cost. The present test data generation scheme generates test cases which satisfy transition path coverage criteria, path coverage criteria and action coverage criteria. A case study on Railway Ticket Vending Machine (RTVM) has been presented to illustrate our approach.

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

When ASICs are dedicated to highly dependable applications, concurrent checking and/or fault-tolerance capabilities are necessary on chip. In particular, FSMs must be protected against permanent and transient faults. The authors review the main proposals one can fine on this subject in the literature. Then, an approach is proposed to achieve intrinsic fault tolerance. This approach is based on a specific logic synthesis for FSMs described by their state transition graph. >