Testability driven synthesis of interacting finite state machines

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

Until now, simulation has been the primary approach for the functional verification of register transfer level (RTL) circuit descriptions written in a hardware description language (HDL). A finite state machine (FSM) coverage test can find all the bugs in a FSM design. However, this is impractical for large designs because of the state explosion problem. In this paper, we modify the higher-level FSM models used in other applications to replace the FSM model in the FSM coverage test. The state transition graphs (STGs) can be significantly reduced in this model, so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically, with little computation overhead. Experimental results show that it is indeed a promising functional test for FSMs.

A popular approach to reduce power consumption is to identify self-loops in a state transition graph (STG) of a finite state machine (FSM) followed by gating the clock with a suitable function to power down the circuit (implementation of the FSM) during the self-loop cycles. Although this approach is effective in circuits with plenty of self-loops, it fails for FSMs without self-loops. Since self loops may not be inherently present in a given FSM, we decompose it into interacting FSMs such that they have plenty of self-loops. In this paper we present a novel partitioning algorithm to decompose a given finite state machine. By using this approach, we could save upto 71% of the total power on circuits like fetch, where other techniques could not save any power.

(Self-)reconfigurable finite state machine (FSM) had been introduced as a formal model to implement the sequential circuit which can be reconfigured during the operation. The reconfiguration is initiated by the external events or by the controller that generates the reconfiguration transitions. In this paper, we optimize the number of reconfiguration transitions required to reconfigure a given FSM into a new target FSM. A serious limitation of previously proposed techniques is that they depend on the number of essential transitions which are the different transitions between a given and a target FSMs. In this paper, we propose a new technique based on FSM decomposition to decompose a given and target FSMs into two sub machines. A part of essential transitions is implemented as a single decomposed submachine with the same functionality in two decomposed FSMs. This submachine is inactive and has no effect in the normal operation but reduces the number of essential transitions during the reconfiguration. We give a decomposition strategy, realize the proper hardware, and provide a set of experimental results that shows the reconfiguration transitions can be substantially reduced, in some cases up to 54%

Implicit state enumeration is used in developing strategies to solve key problems in sequential logic synthesis and test. It is shown that it is possible to extract implicit state transition graphs (ISTGs) from logic-gate and flip-flop descriptions of sequential circuits that allow equivalent states to be represented by cubes, and edges from different states to be coalesced into one, thereby decreasing significantly the CPU time and memory requirements of the extraction process. Coupled with the enumeration technique, synthesis strategies are proposed for FSMs (finite state machines) described at the logic level. As is illustrated, these synthesis strategies allow the authors to optimize large FSMs. The authors apply an ISTG traversal algorithm for verifying equivalence and detecting redundancies in logic-level sequential circuits. This algorithm is more efficient than previously developed sequential test generation algorithms when used to detect equivalent-state redundancies present in some classes of circuits. >

The authors develop optimal synthesis procedures for interacting nonscan sequential circuits composed of interacting finite state machines. For each of the different classes of redundancies, the authors define don't care sets, which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. It is shown that notions of sequential don't cares and conditional compatibility are required to eliminate redundancies. Using a complex don't care set in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable single or interacting finite-state machines (FSMs). Preliminary experimental results indicate that irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times with optimal logic synthesis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Finite state machine (FSM) plays an important role in digital circuit design. Since it stores the system states and controls system functionality, security vulnerabilities of FSM have been exploited extensively. Among the potential attacks, fault inject attack (FIA) is one of the most severe and most challenging to defend against. Unlike existing countermeasures, we propose a novel structure for FSM state flip flop design that can mitigate any kind of timing based FIAs. Our key idea is to sample the flip flop input signals multiple times during one clock cycle, and then compare these values to determine the correct one. This can effectively defeat all the FIAs based on violating FSM state setup time constraint. In addition, such design will make the design more robust against jitters. In order to reduce the design overhead, we use the low-cost transmission gates to implement the proposed latch and flip flop. We use Hspice to simulate the error conditions with delayed input data and jitter and the results confirm that our design is error resilient. We also implement the FSM in AES with our proposed flip flops and compare the area overhead with existing FIA countermeasures. Results show that the two state-of-the-art approaches have 2X and 4X area overhead than ours.

A graph-based reflexive artificial chemistry

This paper presents a finite-state machine (FSM) reengineering method that enhances the FSM synthesis by reconstructing a functionally equivalent but topologically different FSM based on the optimization objective. This method enables the FSM synthesis algorithms to explore a set of functionally equivalent FSMs and obtain better solutions than those in the original FSM. To demonstrate the effectiveness of the proposed method, we apply it to popular power- and area-driven FSM synthesis algorithms, respectively. Our method achieves an average of 5.5% power reduction and 2.7% area reduction, respectively, on 25 Microelectronics Center of North Carolina (MCNC) FSM benchmarks, where the proposed method is applicable. This is a significant performance improvement for the power- and area-driven FSM synthesis algorithms being used. Our method has a negligible run-time overhead, and it maintains the quality of the synthesis solutions.

The authors develop a method based on the premise that optimal state assignment corresponds to finding an optimal general decomposition of a finite state mechanism (FSM). They discuss the use of this approach for encoding state transition graphs extracted from logic-level descriptions. The notion of transition pairing is used to decompose a given FSM into several submachines such that the state assignment problem for the submachines is simpler than the original problem, attempting to avoid compromising the optimality of the solution. A novel decomposition algorithm that can decompose a FSM into an arbitrary number of submachines and a novel constraint satisfaction algorithm to encode the different submachines are given. Experimental results validate the use of decomposition-based techniques to solve the encoding problem. >

NooJ is a linguistic development environment that allows linguists to construct large linguistic resources of the four types in the Chomsky hierarchy. NooJ uses a bottom-up, “cascade” approach to sequentially apply these linguistic resources: each parsing operation accesses a Text Annotation Structure, and enriches it by adding or removing linguistic annotations to it. We discuss the drawbacks of this approach, and we present a new approach that requires that all NooJ linguistic resources be represented by a single type of finite-state machine. In order to do that, we must solve theoretical problems such as “how to handle Context-Sensitive Grammars with finite-state machines”, as well as some engineering problems such as “how to compose sets of large dictionaries and grammars into a single finite-state machine”. Our first experiments show that although that composing large finite-state machines is extremely costly theoretically, the fact that linguistic resources in a typical NooJ cascade depend on each other heavily keeps the size of all intermediary machines manageable. Once the final resulting finite-state machine has been compiled and loaded in memory (e.g. on a webserver) it can be used to parse large texts in linear time.

This paper presents the techniques of implicit traversing and state verification for sequential finite state machines (FSMs) based of on the state collapsing of state transition graph(STG). The problems of state designing are described. In order to achieve high state enumeration coverage, heuristic knowledge is proposed.

This paper presents a new algorithm for scheduling control-dominated designs during high-level synthesis. Our algorithm can schedule systems with arbitrary control flow, including conditional branches and multiple loops. It can handle both upper bound and lower bound timing constraints. The timing constraints can cross basic block boundaries, span different iterations of a loop, and form interlocking cycles in the control flow. A scheduling problem is described by the behavior finite-state machine model, an automaton model for the behavioral specification and synthesis of control-dominated systems. We optimize the performance of the produced digital circuit implementation by minimizing the execution time of each state transition in the state transition graph. The finite-state machines (FSM) scheduling algorithm is based on previous work on cylindrical layout compaction; we extend that work to handle upper bound constraints, allow multiple loops, and not require an initial feasible solution. Experimental results for examples derived from real designs and benchmark descriptions demonstrate that the algorithm can handle complex combinations of constraints very efficiently.

Detection and classification are two significant tasks for industrial fault diagnosis. However, conventional methods typically treat these tasks as separate and independent problems, and necessitate a retraining process when new fault samples or classes are collected. Therefore, an incremental support vector data description scheme using Gaussian kernel function is pro-posed for industrial process fault diagnosis in a unified frame-work. In this framework, the decision boundary is updated incrementally only based on the specific original support vectors and newly collected samples. An adaptive threshold and a restructured radius are proposed to promote accuracy in the fault detection. In the classification procedure, the hyperspheres for all known classes are constructed by decision tree. The new sample that does not belong to any known class is identified as an unknown class. Without a time-consuming retraining process, the proposed diagnosis method with the incremental learning capability can synchronously achieve the fault detection and classification task. Experimental results demonstrate the effectiveness and superiority in terms of diagnosis performance. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —In practical industrial processes, new fault samples are collected and new fault classes emerge continually. Under such scenarios, fault diagnosis with incremental learning capability is becoming increasingly important. This work proposes a unified incremental framework for fault diagnosis based on support vector data description, which is able to achieve fault detection and classification synchronously. For fault detection, an adaptive threshold and a restructured radius are developed. For fault classification, hypersphere-shaped boundaries of all fault classes are given via the decision tree-based strategy. The proposed method is updated to include new fault samples and fault classes without dimensionality reduction or any distributional assumptions.

Current industry design tools and design flow are developed to improve system performance in terms of speed, size, and power consumption. With security and trust becoming more important for system design, how much can we trust the systems built by these tools? In this chapter, we first give motivational examples to show the potential trust vulnerabilities. Then we focus our investigation on sequential system design from the perspective of finite state machine (FSM). We define the notion of trusted FSM both in the most general sense and specifically when state reachability is used as the trust metric. We give a set of necessary and sufficient conditions to build trusted systems in both cases. More specifically, we find that the traditional FSM synthesis procedure will introduce trust vulnerabilities and cannot guarantee any the logic implementation of the FSM to be trusted. Indeed, we show that not only there exist simple and effective ways to attack a sequential system, it is also possible to insert hardware Trojan into the design without introducing any significant design overhead. We then propose a novel practical approach to designing trusted circuits from the FSM specification. We demonstrate both our findings on the security threats and the effectiveness of our proposed method on the MCNC sequential circuit benchmarks.