Reliability research and design of GaN-based three-phase inverter circuits for servo drives considering bridge arm crosstalk

The reliability tests play more and more important role in mechanical systems. A new method named a few samples and combined the probability and the fuzzy mathematics has been set up to explore the unknown system of a few samples with the help of the life samples of the known probabilistic distribution. The method reduced the traditional reliability test samples by some auxiliary information. It converted lots of reliability test into a few samples. This paper introduced two engineering examples to verify the method as an effective way to carry out the reliability tests. It provides the theory basis for the reliability of complicated mechanical systems. The loss caused by fatigue failure is as high as 3%~4% of Gross National Product. Fatigue fracture owned to the cycle load accounts for 95% of the total number of mechanical structure failure. Unfortunately no evidence of failure is observed when fatigue failure reaches its life. This causes human casualties and great economic loss. So the reliability research on complicated mechanical systems has to realize from reliability assessment to the active reliability design. One of the key problems of the active reliability design for complicated mechanical system is to reduce the great waste of the resources used in the probability reliability test. For example, dozens of the high precision gears made of certain material may be run out in the fatigue test which would be running day and night for several months. It has been described many methods about system reliability design in the former research [1-3]. But for many high technological products and important mechanical devices, it is impossible to get the test sample to carry out probability analysis. To exert the advantages of the active reliability design and to realize the green reliability design [4], the only way is to study small samples in the reliability tests and to develop new technique. It is named as a few samples reliability tests method of the complicated mechanical systems.

Reliability research is conducted by many organizations in government, academia and industry. A research roadmap developed collaboratively by the reliability community and led by the Aerospace Vehicle Systems Institute (AVSI) will result in a broad-based, common approach to predicting the reliability of electronics. Research that is proposed in accordance with the roadmap will build on existing results and engage experienced reliability researchers to leverage limited research funds. Future projects will develop the capabilities identified by the roadmap for a reliability prediction methodology that provides accurate, timely and necessary information to support reliable system design. New models and modeling methods will provide the capabilities needed to develop future systems; and will establish a normative basis for future industry and military standards.

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

The effects caused by variability, temperature, radiation or aging may compromise the reliability of electronic circuits. Circuits designers must consider their combined effects early during the design cycle, even though it is a time and effort demanding task. In this work we present a methodology and simulation framework for the reliable design of circuits working under realistic conditions such as a wide range of temperatures, radiation and process variations. This proposal provides an alternative method for validating digital and analog circuits. Depending on the analyzed circuit functionality, the user is able to define complex reliability metrics such as signal upsets, delays or frequency deviations to measure the circuit response in affordable simulation time.

The impact of research and representation of site analysis for creative design approach in architectural design studio

The aim of this paper is to propose a robust reliable bi-objective supply chain network design (SCND) model that is capable of controlling different kinds of uncertainties, concurrently. In this regard, stochastic bi-level scenario based programming approach which is used to model various scenarios related to strike of disruptions. The well-known method helps to overcome adverse effects of disruptions and extend a network that is less vulnerable regarding disruptions strike. Also, scenario-based modeling approach enables decision makers (DMs) to the model uncertainty of model parameters regarding different scenarios that are disregarded in reliable SCND research scope. An effective robust programming method is employed to control the risk-aversion level of output decisions that helps company managers to adjust long-term effects of their decisions via determining uncertainty level of model parameters. Notably, extended bi-objective programming model minimizes total costs of network design aside with maximization of responsiveness of supply chain network. Agile and fast performing networks could be regarded as a long-term competitive advantage for companies that are modeled in the extended form as a different objective besides cost minimization. Finally, the extended robust reliable network model is implemented and evaluated based on real case study of a national project and output results demonstrates efficiency and applicability of proposed reliable network.

Networked embedded systems (NES) researchers tend to have a general vision of these systems as being low cost, autonomous, pervasive, invisible and reliable. A proactive, integrated approach to reliability analysis and planning with a vision towards future applications is therefore essential if NES are to be accepted in the marketplace. As overall NES reliability is a distributed function across all layers of the protocol stack, each layer must look not only at its individual responsibilities for reliability but also at how design decisions at any individual layer interact with other layers to effect overall reliability and, in a co-design approach, at what information must be provided to, and requested from, other layers of the stack to allow optimising of overall reliability. This is not a trivial challenge and, yet, it is one which receives comparatively little attention in NES research programmes. In this chapter, the issue of NES reliability is examined primarily in the context of the systems hardware, principally the node, and the associated reliability research challenges are discussed. While there is much to be learnt from past research on reliability research in distributed systems, mobile devices and wireless networks, NES present extra challenges which need to be more actively and proactively considered at this still relatively early stage in global NES research. Retrospective reliability improvement is always considerably more difficult, expensive and less effective than using a proactive design for reliability approachKeywordsNetworked Embedded SystemsReliabilityWireless Sensor NetworksHeterogeneous System-in-a-PackageStressesStrengthsFailure MechanismsSensor Node Lifetime

Progress in reliability research in the micro and nano region

This section represents the more practical aspects of the new mechanics (XM) and the extreme probing capability of the techniques to make a difference in the advanced and emerging materials at small scale and in real (industry-relevant), advanced devices and structures. Chap. 4: Recent Cases in Advanced Micro/Nanoelectronics, Microsystems and MEMS Devices and Technologies consists of recent cases in which new insights of XM have continued to enable Design for Reliability (DfR) in the Through-Silicon Vias (TSV) technology for 3D Integrated Circuits (IC) design and in the fabrication and plasticity of low-melting metal nanostructures for advanced nanotechnological system design. In addition, unique mechanoelectrical behaviors of Cu/Nb nanolayered structures were revealed with potential applications in Structural Health Monitoring (SHM) and yet another important DfR application in enabling next technology nodes in the semiconductor industry roadmap (ITRS/International Technology Roadmap for Semiconductors).

Solar energy is one of the renewable energy that has a large potential in Indonesia. Solar energy can be converted into electrical energy using PV. According to the increasing energy demand in Indonesia and the enactment of the feed-in tariff by the government, it will be easier for the sale and purchase of electricity through the on-grid system. This study discusses the design and implementation of a three-phase grid-connected inverter. This three-phase inverter circuit uses sinusoidal pulse width modulation for input signal (SPWM) is used to input the IR2113 circuit a three-phase inverter driver. SPWM used is also a synchronization method to connect the inverter to the grid. Grid synchronization in this study is equating the phase angle and inverter output frequency to the grid. In this design add DC to DC converter type push-pull converter as a three-phase inverter supply and also as a control to adjust the inverter output voltage to fit the grid. The push-pull converter uses an SG3525 PWM IC generator. The circuit can be adjusted according to the voltage you want to produce. The circuit uses a high-frequency transformer as a step up the voltage. The result of the system design is the PV output voltage is increased by the push-pull converter and then to supply threephase inverter.

The escalating volume of plastic waste has become a critical environmental challenge, highlighting the need for innovative solutions to repurpose it into valuable construction materials. This study aimed to design and develop a pneumatic-based eco-paving block printing machine that uses plastic waste as its primary raw material. The research methodology encompassed the design and simulation of pneumatic circuits, structural analysis involving stress distribution, displacement, and factor of safety (FOS), and strength testing of the fabricated eco-paving blocks. The machine was equipped with a pneumatic cylinder measuring 80 × 75 mm, operating at a pressure of 6 bar and generating a maximum pressing force of 300 kg. The simulation results confirmed that the maximum stress and displacement remained within safe limits, with a minimum FOS of 8.4, thereby ensuring a stable and reliable design. Testing of the eco-paving blocks revealed compressive strengths ranging from 38 to 54 MPa, surpassing the requirements of the SNI 03-0691-1996 standard. This study demonstrates that a pneumatic-based eco-paving block printing machine effectively transforms plastic waste into high-quality construction materials compliant with national standards, offering a practical solution to the plastic waste crisis while promoting sustainability in the construction industry.

A new design methodology for knowledge-based analogue IC design is presented. Due to the nonlinear nature of the analogue design process, iterations are always necessary to achieve accurate and reliable designs. A prototype expert system design assistant and a conventional circuit simulator are used for the iterative design process. The expert system employed is capable of optimising circuit topologies, as well as circuit element geometries, to better satisfy the performance specifications. Circuit reconstruction is achieved through circuit primitive replacements and design equation substitutions. Circuit primitive and critical nodes are processed before layout generation to minimise undesired parasitic effects. Layout parasitics can be included optionally in the design optimisation step. Experimental results are shown, to demonstrate the effectiveness of the flexible architecture approach through iteration and the expert analogue design system.

The design for reliability concept is already in use on digital circuits, but not systematically in use on AMS or RF circuits. A reliable circuit design demands knowledge of the physical degradation and models to analyze the reliability in earlier stages. Also, it needs to be simple enough to be used on the redesign. In this work, we propose and validate an AMS and RF circuit design for reliability method. In order to investigate our method, we have designed a 5–3 NOR interpolative Digital Controlled Oscillator (DCO) near 1 GHz applications. This design example has presented 1.4% decrease of oscillation frequency, 0.2% decrease of phase noise for a 1 MHz off-set, and 2.1% decrease of power consumption after 10 years of degradation. According with the trends presented in Table I, we estimate that the f osc ageing degradation was improved of 13 % by applying the design for reliability method.

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The schematic edit and T-Spice of Tanner tools formed the simulation environment.

The existence of multi-dimensional tradeoffs among performance metrics is an impediment to the development of reliable Electronic Design Automation (EDA) tools for the design of analog circuits. To overcome this limitation, soft computing techniques that have functionality similar to the human brain are being explored. This work proposes a methodology for the development of a fast and accurate Artificial Neural Network (ANN) model for analog circuits, to achieve optimization of its design, considering a 2-stage op-amp for illustration. In order to map complex and multiple input-output relationships of analog circuits, an ANN architecture of a single hidden layer with its neuron count selected to be between the number of neurons in the input and output layers is proposed. The ANN model is developed in the MATLAB environment, and trained using SPICE-generated performance dataset. For a given set of performance metrics, the ANN model generated designs are validated against SPICE simulations. It is demonstrated that trained ANN models substitute the circuit simulator, to achieve design optimization, in a single iteration, for a new set of design specifications.