Reliable design methodology: The combined effect of radiation, variability and temperature

Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.

Circuit reliability due to Bias Temperature Instability, BTI, has become an important concern in scaled-down complex electronic systems. Even more, current silicon technologies are severely affected by the combined impact of BTI-induced device’s aging and Process-induced device’s parameters variations. The conventional worst-case guardbanding to deal with reliable circuit operation is not longer an efficient approach as the circuit performance is significantly penalized. This paper presents a gate-sizing optimization me-thodology to reduce the worst-case guardbanding considering the combined effects of aging due to BTI and process variations. The proposed methodology allows to trade-off the reduction of guardbanding and the area cost. The proposed methodology uses multiple workload-aware aging analysis procedures to identify a realistic workload condition that causes maximum degradation to each potential critical paths of the circuit. In such a way, classic worst-BTI assumptions that lead to over-design are avoided. New gate-sizing metrics are proposed to identify the most beneficial gates to resize in the delay optimization process. In order to compute the gate sizing metrics efficiently, it is proposed a fast approximation for the sensitivity of the statistical delay of a path with respect to a change in the size of a gate. Also, the criticality, slack-time and area penalization are considered in the metric. A heuristic is proposed to guide the iterative delay optimization process. Some key conditions are identified in the workload analysis, metric evaluation and the heuristic to reduce the computational cost. The results show clearly the benefits of using multiple workload-aware aging analysis and the proposed gate-sizing metrics. It is shown that the proposed gate-sizing metrics are more efficient than others available in the literature since they provide a better area-guardband reduction trade-off. The proposed methodology results in more reliable designs at low area overhead, and it is suitable to guarantee the stringent quality requirements of modern circuits.

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to "design-in" quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits.

Flexible electronics are possible alternative for portable consumer applications with many advantages. However, the circuit design for flexible electronics is still challenging, especially for sensitive analog circuits. Significant parameter variations and bending effects of flexible TFTs further increase the difficulties for circuit designers. In this paper, an automatic circuit sizing technique is proposed for the analog circuits with flexible TFTs. The process variation and bending effects of flexible TFTs are considered simultaneously in the optimization flow. As shown in the experimental results, the proposed approach can further improve the design yield and significantly reduce the design overhead.

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CADsEDA industry professionals, academics and students.

The concept of chip-to-chip information propagation by spoof surface plasmon polariton (SSPP) meta-surface at terahertz frequency has been introduced of late, that promises data transfer with high bandwidth, low crosstalk, and low energy consumption. As the exotic electromagnetic properties of the metasurface derive from its designed geometric pattern and periodicity, any possible variation of fabrication process parameters may affect the design pattern and consequently the information capacity of SSPP interconnects. In this work, we have investigated the extent of performance degradation of SSPP interconnect with the statistical variation of geometric pattern of the metasurface. We also described the technique of the design of appropriate analog circuit so that the loss of signal integrity incurred by the process variation can be recuperated in real time.

Integrated circuit technology has been dramatically developed during the past decades. Reliability of analog circuits becomes more and more important for yield design. However, most state of the art researches are concentrated on analog circuit robust optimization and analog circuit fault detection. There are seldom any researches on analog circuit fault-tolerant design. This paper proposed an negatively-correlated evolution strategy to design fault-tolerant analog circuits. In the proposed strategy, the fault-tolerant circuit can be considered as an ensemble system. The system contains several child circuits. negatively-correlated evolution strategy automatically synthesizes these child circuits, and make sure the errors of each child circuits are negatively correlated to each other. The experimental result shows that, in most circumstances, the circuit with negative correlation redundancy has the best fault tolerant performance compared with the circuit with randomly generated redundancy. The the circuit with duplicated redundancy didn't has much improvement compared with single circuit. So, the proposed strategy is a beneficial idea towards robust and fault tolerant analog circuit design.

Thin and thick film materials are widely used in modern electronic circuits due to their ability to provide miniaturization, high performance, and cost-effective production. Thin film technology involves depositing layers of conductive, resistive, and dielectric materials onto a substrate, typically using methods like vacuum deposition or sputtering. Thick film technology, on the other hand, uses a screen-printing process to deposit paste-like materials onto substrates and is known for its durability and adaptability to harsh environments. Both technologies play crucial roles in designing analog and digital circuits, especially in fields like telecommunications, automotive electronics, and medical devices. The increasing demand for smaller, faster, and more efficient electronic devices has put pressure on the development of high-performance circuits using thin and thick film technologies. A key challenge is optimizing material properties to balance electrical performance, thermal management, and mechanical reliability in both analog and digital circuits. This study explores the design and performance evaluation of analog and digital circuits using thin and thick film materials. Thin film circuits were fabricated using sputtering techniques to deposit layers of resistive and conductive materials with precise thickness control. Thick film circuits were created by screen-printing conductive, resistive, and dielectric pastes onto ceramic substrates. Electrical performance was tested for both types of circuits, focusing on parameters such as resistance, capacitance, and inductance. The thin film circuits demonstrated superior electrical performance with lower parasitic inductance and capacitance, achieving a resistance tolerance of ±1% and a thermal coefficient of resistance (TCR) of ±50 ppm/°C. The thick film circuits, while having slightly higher parasitic values, offered robustness and mechanical stability in high-temperature environments, with TCR values ranging from ±100 to ±250 ppm/°C. Both technologies showed significant promise, with the choice of material depending on the specific application requirements for analog and digital systems.

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization.

Defects and faults arise from physical imperfections and noise susceptibility of the analog circuit components used to create digital circuits resulting in computational errors. A probabilistic computational model is needed to quantify and analyze the effect of noisy signals on computational accuracy in digital circuits. This model computes the reliability of digital circuits meaning that the inputs and outputs and their implemented logic function need to be calculated probabilistically. The purpose of this paper is to present a new architecture for designing noise-tolerant digital circuits. The approach we propose is to use a class of single-input, single-output circuits called Reliability Enhancement Network Chain (RENC). A RENC is a concatenation of n simple logic circuits called Reliability Enhancement Network (REN). Each REN can increase the reliability of a digital circuit to a higher level. Reliability of the circuit can approach any desirable level when a RENC composed of a sufficient number of RENs is employed. Moreover, the proposed approach is applicable to the design of any logic circuit implemented with any logic technology.

Uncertain and unpredictable faults can occur in electronic systems that work in harsh environments. Analog circuits play an important part in modern electronic systems. Accordingly, it is important to investigate the reliability of analog circuits under uncertain faults. For robust analog circuits designed to be tolerant of certain faults, unexpected faults might issue great influence. For the enhancement of analog circuits' robustness generalization on unexpected and uncertain faults, this paper presents a new idea to evolve analog redundancies that are negatively correlated. An evolutionary negative-correlation framework is proposed to evolve negatively correlated redundancies. An experimental study is provided to observe the reason why the proposed framework is able to evolve negatively correlated results. In Section IV, we implement various fault simulations to statistically test and evaluate the fault-tolerant performance of the proposed negatively correlated redundancies under uncertain faults. Experimental results show that negatively correlated redundancies significantly improve the analog circuit's fault-tolerant performance under uncertain-fault environments in two aspects: 1) negatively correlated redundancies have lower performance degradation in the statistical evaluation after various fault simulations, and 2) negatively correlated redundancies have better stability in the face of unpredictable faults. A significant improvement is that negatively correlated redundancies have more outstanding robustness on various uncertain faults than analog circuits that are designed for certain faults. By this token, the proposed idea can be a promising way of robust analog circuit design for uncertain-fault environments.

In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonov's functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis method. The new algorithm can give transient lower bound and upper bound of the performance variations affected analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method.

Metal-oxide based bipolar Resistive RAM (RRAM) is one of the most promising candidates for the future non-volatile data storage. Due to unique properties e.g., small footprint, ability to modulate resistance states in wide ranges dynamically, hysteresis and CMOS compatibility, RRAM can be a fruitful candidate for analog circuit design. However, the recent literature only scratches the surface of this interesting prospect. In this paper, a single RRAM behavior is studied under temperature, voltage and process variations from an analog design standpoint. A comparative study is performed between two analog circuits namely, Common Source (CS) amplifier and differential amplifier with traditional passive resistors and with passive resistors replaced by RRAM along with two other design examples, namely constant <inline-formula><tex-math notation="LaTeX">$g_m$</tex-math></inline-formula> biasing circuit and active low-pass filter, where RRAM can be integrated into analog circuits. Our study shows that blind swapping of passive resistors with RRAM in analog circuits can actually degrade the performance metrics. We propose techniques such as usage of RRAM Low Resistance State (LRS) to recover the loss. We also note that hyperbolic I-V characteristics of RRAM can inherently improve the linearity of RRAM based analog designs. Simulation results indicate that RRAM based amplifiers can achieve 2X area reduction, about 1.5X higher bandwidth with only <inline-formula><tex-math notation="LaTeX">$\approx 9\%$</tex-math></inline-formula> reduction in gain. The resistance modulation property of RRAM is applied to realize a source degenerated amplifier with reconfigurable linearity, to a constant transconductance bias circuit to avoid resistance trimming and to design a programmable active low pass filter.

4 - Analog Design Productivity and the Challenge of Creating Future Generations of Analog Engineers

Critical transistors nexus based circuit-level aging assessment and prediction