Time-domain performance bound analysis of analog circuits considering process variations

In this article, we propose a new parallel matrix solver, which is very amenable for Graphic Process Unit (GPU) based fine-grain massively-threaded parallel computing. The new method is based on the graph-based symbolic analysis technique to generate the computing sequence of determinants in terms of determinant decision diagrams (DDDs). DDD represents very simple data dependence and data parallelism, which can be explored much easier by GPU massively-threaded parallel computing than existing LU-based methods. The new method is based on the hierarchical determinant decision diagrams (HDDDs). Inspired by the inherent data parallelism and simple data dependence in the evaluation process of HDDD, we design GPU-amenable continuous data structures to enable fast memory access and evaluation of massive parallel threads. In addition to parallelism in DDD graph, the new algorithm can naturally explore data independence existing in Monte Carlo and frequency domain analysis. The resulting algorithm is a general-purpose matrix solver suitable for fine-grain massive GPU-based computing for any circuit matrices. Experimental results show that the new evaluation algorithm can achieve about two orders of magnitude speedup over the serial CPU based evaluation and more than 4× speedup over numerical SPICE-based simulation method on some large analog circuits.

This paper presents a state-of-the-art review of the recent advances in computer methods for analysis and design of switched circuits in both time and frequency domains. It also presents new research results on time-domain analysis and sensitivity of switched nonlinear circuits, time- and frequency-domain statistical analysis of switched linear and nonlinear circuits, and efficient modeling and analysis of clock feedthrough and charge injection in switched linear circuits. In time-domain analysis, the modeling of switches and its effect on the simulation of switched circuits are investigated. Formulation methods for these circuits are examined. Inconsistent initial conditions arising from ideal switching are investigated and numerical methods that derive the consistent initial conditions are examined. Sampled-data simulation (SDSIM) of switched linear circuits including clocked sigma-delta modulators is investigated. SDSIM is extended to switched nonlinear circuits. Time-domain sensitivity of switched linear and nonlinear circuits is analyzed using SDSIM. Efficient time-domain statistical analysis of switched linear and nonlinear circuits is introduced, and their effectiveness is assessed using Monte Carlo simulation. Methods that compute the effect of the clock jitter of periodically switched linear (PSL) circuits are examined. Time-domain noise analysis of PSL circuits is investigated. In frequency-domain analysis, exact frequency analysis of multiphase PSL circuits is reviewed. Sensitivity analysis of these circuits is examined in detail. Adjoint network theory and its usefulness in noise and sensitivity analysis of switched linear circuits are studied. Group delay of PSL circuits is investigated briefly. Efficient modeling and analysis of clock feed-though and charge injection of PSL circuits are introduced. Distortion and sensitivity of periodically switched nonlinear circuits with mild nonlinearities are investigated. Finally, frequency-domain noise analysis of PSL circuits is examined.

This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction by deriving the exact or approximate admittances in rational form in the reduced circuit matrix and deriving the circuit characteristics for very large linear analog and interconnect circuits. We characterize some theoretical results regarding the conditions on the generations of canceling terms during the general hierarchical circuit analysis and propose an explicit de-cancellation scheme to remove canceling terms based on a new hierarchical symbolic analysis framework. The resulting algorithm can be used for modeling and simulation of linear analog and interconnect circuits in both frequency and time domain.

Magnetostrictive guided waves are widely used in nondestructive testing and structural health monitoring of pipes to ensure their integrity. These guided waves are mechanical waves, and if the natural frequencies of the pipe are used as excitation frequencies, the mechanical vibration amplitude can be enhanced, which will then improve the amplitude of the guided waves. Comparison of the various methods to determine the natural frequencies of pipes shows that the white noise signals remain relatively smooth in both time and frequency domains. White noise has a wide bandwidth and uniform energy distribution. It does not require high energy within a short time period, so it is easy to generate. In this article, white noise is used to determine the natural frequencies of pipes. Comparison of the white noise spectra produced by analog and digital circuits shows that the energy spectrum of white noise produced by the analog circuit is high and uniform, so the analog circuit is used as the white noise source and this noise is loaded onto a magnetostrictive sensor. The detected signal spectrum is then analyzed and the frequencies with high power density spectra are determined to be the natural frequencies. The natural frequencies of the pipeline detected using white noise are compared with the results of modal analysis. Simulation results and experimental results demonstrate that the use of white noise allows the natural frequencies of pipes to be determined quickly and accurately. These natural frequencies can be used in magnetostrictive guided-wave nondestructive testing.

This paper describes CODAC, a CAD tool for characterization and analysis of analog and digital circuits. It is based primarily on the industry standard electrical simulator, SPICE. CODAC provides a powerful C like language for specifying the characterization problem. In addition to providing an extensive library of built-in analysis functions it also supports a procedural interface that facilitates the definition of customized analysis functions. A capability to distribute in parallel the large number of simulation runs for an extensive circuit analysis (e.g. Monte Carlo analysis) is provided which significantly reduces overall cycle time. CODAC is being successfully used for circuit analysis and as a part of analog and digital library development flow at Texas Instruments.

During fabrication process, mixed analog and digital integrated circuits (ICs) are more susceptible to process variations and physical defects than pure digital ICs. Therefore, it is beneficial to simulate the effects of process variations and defects on mixed-signal designs even before the design goes into production. Simulations of ICs having process variations are performed with Monte Carlo simulations. And, simulations of ICs having physical defects are called fault simulations. However, both simulation schemes require large numbers of instances. Consequently, simulation times can be extremely long, e.g. hours or days. In this System-on-a-Chip (SoC) era, mixed-signal designs are becoming more complex and thus impossible for traditional simulation schemes to be effectively applied. To dramatically reduce Monte Carlo simulation time and fault simulation time, a new behavioral simulation approach is proposed in this dissertation. Essentially, timing consuming detailed circuit simulations can be replaced by simple linear equations. A flash analog-to-digital converter (ADC) is used here to demonstrate the feasibility of proposed approach. The behavioral models for the flash ADC having process variations and physical defects are built. With these behavioral models, behavioral simulation programs are written in C++ to perform fast Monte Carlo simulations and fault simulations. For the small 3-bit flash ADC, the proposed method reduced the Monte Carlo simulation time, with 30 instances, from 180 hours to a mere 15 minutes. Such dramatic reduction in simulation time was achieved with a maximum prediction error of no more than 6%.

Fast and accurate collision probability computations are essential for protecting space assets. Monte Carlo (MC) simulation is the most accurate but computationally intensive method. A Graphics Processing Unit (GPU) is used to parallelize the computation and reduce the overall runtime. Using MC techniques to compute the collision probability is common in literature as the benchmark. An optimized implementation on the GPU, however, is a challenging problem and is the main focus of the current work. The MC simulation takes samples from the uncertainty distributions of the Resident Space Objects (RSOs) at any time during a time window of interest and outputs the separations at closest approach. Therefore, any uncertainty propagation method may be used and the collision probability is automatically computed as a function of RSO collision radii. Integration using a fixed time step and a quartic interpolation after every Runge Kutta step ensures that no close approaches are missed. Two orders of magnitude speedups over a serial CPU implementation are shown, and speedups improve moderately with higher fidelity dynamics. The tool makes the MC approach tractable on a single workstation, and can be used as a final product, or for verifying surrogate and analytical collision probability methods.

Integrating analog and radio-frequency (RF) circuits with digital blocks on a C M O S system-on-a-chip (SoC) has drawn a lot of attention, recently. One major obstacle at this high level of integration is the substrate noise, which results in undesired interaction between these circuits through the common substrate. Analog circuits are the main victims of such interactions; consequently, understanding the behaviour of substrate noise and performance degradations it causes, is indispensable for analog designers. This work addresses three aspects of substrate noise. First, substrate noise is characterized in the time and frequency domains to identify major parameters that control substrate noise generation, propagation, and reception. Effects of many parameters on the amount of noise generation and coupling are also studied. Second, this thesis investigates the noise impact on analog circuits from a circuit-level point of view by introducing a new small-signal model of the M O S device, which accounts for the substrate noise effects. While most works have focused on system-level or signallevel analysis, study of the noise from a circuit-level point of view is more beneficial for analog designers because it gives them more insight on how to improve the substrate noise rejection capability of their designs. Finally, noise reduction techniques are revisited in this work. The use of passive guardrings is reviewed in detail and the effects of many design parameters on the amount of noise attenuation provided by these structures are studied. The behaviour of guard-rings in different substrates are also discussed.

Time–frequency analysis (TFA) methods can characterize the instantaneous frequency (IF) features of nonstationary signals by constructing the time-domain signal model. However, the traditional TFA methods are ineffective for transient signals that are discontinuous in the time domain and characterized by sharp frequency variation. Therefore, this article proposes a new TFA method called generalized transient-squeezing transform (GTST) to process transient signals by constructing a signal model in the frequency domain. First, the generalized group delay (GD) estimation is calculated based on the frequency-domain signal model. Then, the generalized transient-squeezing operator is constructed by iterative operations. Finally, the time–frequency (TF) energy is rearranged according to the constructed operator. The GTST provides a more compact TF representation (TFR) of the transient signal while maintaining reversibility. Numerical validation shows that the proposed method has higher TF concentration and accuracy in analyzing transient signals compared with other advanced TFA methods. Experimental validation shows the effectiveness of the proposed method in practical transient signal analysis.

In the actual working process of the analog circuit, the probability of multiple component failures at the same time is lower than the probability of a single component failure, which makes the single fault data samples and multiple fault data samples tend to show imbalanced characteristics. However, most of the existing data-driven analog circuit diagnosis methods focus on the balance data sample set. Therefore, it is hard to satisfy the needs of fault diagnosis during the actual working of analog circuits. In response to the problems raised above, an analog circuit fault diagnosis method based on enhanced boundary equilibrium generative adversarial network (EBEGAN) is proposed. The generator of boundary equilibrium generative adversarial networks (BEGAN) uses conditional variational auto encoder (CVAE), which can enhance the generated sample quality while ensuring sample diversity. In addition, by introducing the classified loss factor into the loss function, the discriminator has the ability to distinguish the true and false and the type of samples. The experimental results indicate that this study proposes the new method in the situation of imbalanced data, the type of fault in the analog circuit can be accurately identified. compared with the existing analog circuit fault diagnosis methods.

Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as (TDCs) and digital to-time converters (DTCs), was not widely adopted until the late 1990s when semiconductor technology advanced to the sub-micrometer region.

Flexible electronics are possible alternative for portable consumer applications with many advantages. However, the circuit design for flexible electronics is still challenging, especially for sensitive analog circuits. Significant parameter variations and bending effects of flexible TFTs further increase the difficulties for circuit designers. In this paper, an automatic circuit sizing technique is proposed for the analog circuits with flexible TFTs. The process variation and bending effects of flexible TFTs are considered simultaneously in the optimization flow. As shown in the experimental results, the proposed approach can further improve the design yield and significantly reduce the design overhead.

Winner-Take- All (WTA) circuit chooses a winner input from a set of input signals. WTA circuits employ transistors that operate in the sub-threshold or weak inversion region. With technology scaling, sub-threshold circuits are prone to mismatch and process variations which degrade the performance of these circuits. This paper presents a novel WTA circuit that employs a CMOS double pair transistor as a translinear element that is more tolerant to mismatch and process variations. Monte Carlo simulations are used to compare the performance of the existing and the proposed topologies to estimate the effects of process and mismatch variations. Results show that the proposed circuit is able to reduce the range of variations by three orders of magnitude compared to original one for similar variations in the transistor parameters. The proposed element also shows better accuracy in replicating the maximum input current compared to the original circuit.

Heart period variability has been considered for clinical assessment of autonomic function, determining the presence of haemorrhage or disease states, and for predicting mortality from traumatic injury. However, for heart period variability to be clinically useful, a number of important methodological issues should be addressed, including the minimum number of R-R intervals (RRI) required for accurate derivation, and the reproducibility of these metrics. ECGs were recorded for > or =10 min in 18 resting, supine subjects (12 M/6 F; 19-55 years). Heart period variability analyses included 21 time, frequency and complexity domain metrics. For assessment of minimum RRIs required, measurements were made from ECG recordings of 5 min down to 30 s for time and frequency domain metrics, and from 800 RRIs down to 100 RRIs for complexity metrics, by methodical truncation of the data set. Inter-subject variability was assessed by calculating the range and co-efficient of variation (%CV) across all subjects. Two independent 30 s or 100 RRI ECG segments were used to assess intra-subject variability via calculation of %CV in each subject. Six time and frequency domain metrics were robust down to 30 s of data, while five complexity metrics were robust down to 100 RRIs. All time and frequency domain metrics (except for RRI) exhibited high inter-subject variability (CVs > or = 30.0%), while five of eleven complexity metrics displayed low inter-subject variability (CVs < or = 8.5%). In the assessment of intra-subject variability in metrics valid with 30 s or 100 RRIs of ECG, only one time domain and four complexity metrics had CVs < 10%. Metrics that are highly reproducible and require few RRIs are advantageous for patient monitoring as less time is required to assess physiological status and initiate early interventions. Based on our analyses from healthy, resting humans, we have identified a select cohort of heart period variability metrics that performed well in regards to these two criteria.

Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.