CODAC-a characterization system for digital and analog circuits

7 - Analog Interfacing

Recent advances in programmable analog circuits have made it possible to consider analog signal processing as an alternative to some digital signal processing. We discuss the use of analog floating-gate devices for signal processing applications. We also discuss the motivation for doing more signal processing in analog circuits before the analog-to-digital conversion. Finally, we present an overview of the trade-offs in implementing functions in analog VLSI vs. digital VLSI; including power consumption, linearity, SNR, and dynamic range in analog and digital circuits for signal processing hardware.

This paper presents a novel digital instrument designed for measuring radiation doses in Ethanol-Chlorobenzene (ECB) dosimeters, based on oscillometry method. ECB dosimeters are versatile tools for radiation measurement, particularly in medical and industrial applications. Various components of the device including measuring cell, analog and digital circuits were designed, simulated, optimized and verified. The measuring cell was manufactured to maximize the sensitivity in detecting changes in the conductivity of the ECB solution inside the ampoules. The analog oscillating circuit was fabricated using new and common elements in the market such as operational amplifiers (Op Amps), diodes and transistors. The oscillator frequency was set to the lowest possible value to reduce the adverse effects of high frequencies. However, further decrease in frequency causes the conductivity changes of the ECB solution to be measured by the analog circuit inefficiently. The digital circuit was designed and constructed to interface with the analog circuit, processing its output voltage. This digital circuit included an ATmega8A microcontroller, a DS18B20 temperature sensor, a graphic LCD, and other widely used integrated circuits (ICs). The overall performance of the apparatus was validated by reading the absorbed dose of a set of dosimeters irradiated at doses of 1, 5, 10, 30, 70, and 100 kGy in the Gamma cell GC-220 of our laboratory. The maximum absolute relative difference between the average dosimeter readouts and expected values was about 7% and the average value of the absolute relative differences at different doses was about 3.3%. The negligible discrepancy between the values read by the manufactured device and the actual values demonstrates the accuracy of the device operation. Therefore, this device can be considered as an appropriate apparatus for reading the ECB dosimeters and can serve as a key component of an ECB dosimetry system for high-dose dosimetry applications.

In this paper, we describe the complete MOSFET model developed for circuit simulations. The model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. The unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. Additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model.

In this paper, we describe the complete MOSFET model developed for circuit simulations. The model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. The unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. Additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model.

Thin and thick film materials are widely used in modern electronic circuits due to their ability to provide miniaturization, high performance, and cost-effective production. Thin film technology involves depositing layers of conductive, resistive, and dielectric materials onto a substrate, typically using methods like vacuum deposition or sputtering. Thick film technology, on the other hand, uses a screen-printing process to deposit paste-like materials onto substrates and is known for its durability and adaptability to harsh environments. Both technologies play crucial roles in designing analog and digital circuits, especially in fields like telecommunications, automotive electronics, and medical devices. The increasing demand for smaller, faster, and more efficient electronic devices has put pressure on the development of high-performance circuits using thin and thick film technologies. A key challenge is optimizing material properties to balance electrical performance, thermal management, and mechanical reliability in both analog and digital circuits. This study explores the design and performance evaluation of analog and digital circuits using thin and thick film materials. Thin film circuits were fabricated using sputtering techniques to deposit layers of resistive and conductive materials with precise thickness control. Thick film circuits were created by screen-printing conductive, resistive, and dielectric pastes onto ceramic substrates. Electrical performance was tested for both types of circuits, focusing on parameters such as resistance, capacitance, and inductance. The thin film circuits demonstrated superior electrical performance with lower parasitic inductance and capacitance, achieving a resistance tolerance of ±1% and a thermal coefficient of resistance (TCR) of ±50 ppm/°C. The thick film circuits, while having slightly higher parasitic values, offered robustness and mechanical stability in high-temperature environments, with TCR values ranging from ±100 to ±250 ppm/°C. Both technologies showed significant promise, with the choice of material depending on the specific application requirements for analog and digital systems.

In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonov's functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis method. The new algorithm can give transient lower bound and upper bound of the performance variations affected analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method.

To verify mixed-signal SoC on the function and behavior level, one of the challenges is how to represent both analog circuits and digital circuits in a consistent model. The reason is that the performance representations of analog circuits and digital circuits are quite different. This paper addresses an innovative logic representation used for analog circuit description. This logic representation is based on the condition parameter and the concept of the efficient function. The analog circuits or system can be described in the efficient function form. Therefore, the consistent verification on functions and behavior of the mixed-signal SoC can be reached.

A prototype system to aid analog design engineers in the synthesis and analysis of CMOS analog circuits has been developed. ACAD (analog computer-aided design) differs from other tools by its extensive use of hierarchy and two-port network theory to subdivide the process of solving the small signal network functions. This allows larger circuits to be analyzed. ACAD solved and simplified all of the two-port network equations for an operational amplifier containing 29 MOS transistors, 2 resistors, and 3 capacitors by analyzing, simplifying, and combining four subcircuits. ACAD produced the correct results for the model being evaluated. These results show that computer-aided hierarchical small signal model analysis of analog circuits is possible.

In this work, we report on the significance of non-overlap channel architecture in nanoscale double gate (DG) FETs to improve performance of low-voltage analog and digital circuits. It is shown that the low-voltage operation of a cascoded Operational Transconductance Amplifier (OTA) and 6-T SRAM cell can be considerably enhanced using underlap gate-source/drain design. The present work provides new opportunities for realizing future low-voltage analog and digital circuits with underlap DG FETs.

Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.

Spacecraft electronics are affected by the space radiation environment. Among the different types of radiation effects that can affect spacecraft electronics is the single event transients. The space environment is responsible for many of the single event transients which can upset the performance of the spacecraft avionics hardware. In this paper we first explore the origins of single event transients, then explore the modeling of a single event transient in digital and analog circuit. The paper also addresses the concept of crosstalk that could develop among digital circuits in the present of a SET event. The paper ends with a brief discussion of SET hardening. The goal of the paper is to provide methodologies for assessing single event transients and their effects so that spacecraft avionics engineers can develop either hardware or software countermeasures in their designs.

Spacecraft electronics are affected by the space radiation environment. Among the different types of radiation effects that can affect spacecraft electronics is the single‐event transient (SET). This chapter explores the origins of SETs and their effects as outlined by many scientists and researchers, many of which are mentioned in the references. It also explores the modeling of a SET in digital and analog circuit. The chapter also addresses the concept of crosstalk that could develop among digital circuits in the present of a SET event. It provides a discussion of SET hardening. The chapter presents a qualitatively methodology for assessing SETs and its effects so that spacecraft avionics engineers can develop either hardware or software countermeasures in their designs. Single‐event effects is the general term used when space energetic particles are capable of creating an electrical response in an electronics device.

Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equation solving. However, analog computing also comes with drawbacks such as its sensitivity to process variation and noise, limited scalability, programming difficulty, and poor compatibility with digital circuits and design tools. We propose to leverage the strengths of analog circuits and avoid its weaknesses by using digital circuits and time-encoded computation. Time-encoded circuits also operate on continuous data but are implemented using digital circuits. We propose a novel scalable general purpose analog processor using time-encoded circuits that is well suited for emerging applications that require high numeric precision. The processor’s datapath, including time-domain register file and function units are described. We evaluate our proposed approach using an implementation that is simulated with a 0.18µm TSMC process and demonstrate that this approach improves the performance of a scientific benchmark by 4x compared against conventional analog implementations and improves energy consumption by 146x compared against digital implementations.

The nullor, as a network element, is very popular in the areas of modeling, synthesis and analysis of analog circuits. Nullors are pathological or singular elements that posses ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. Therefore, in order to compute symbolic expressions of pathological element-base equivalent analog circuits, the nullor properties should be taken into account in the formulation process. Nodal analysis (NA) of these circuits is very popular. However, the recently proposed methods of formulation the nodal admittance (NA) matrix, require many operations on the rows and columns of an initial node admittance matrix (INAM), which has the order (nxn), for the (n+1) node network or a laborious procedure of computation of norator and nullator indexes. This paper presents a new method of formulation of the nodal admittance matrix for linear active circuits with nullors that performs direct construction of the final nodal admittance matrix (FNAM), which has the order (n-k)x(n-k), and uses only classical methods of element stamps. (k is the number of nullators and norators pairs). The viability and the potentiality of the proposed method (of the FNAM) is showcased via application examples. The improved formulation method is compared with other formulation methods, showing that it is simpler.