ACAD: A hierarchical approach to CMOS design analysis

The nullor, as a network element, is very popular in the areas of modeling, synthesis and analysis of analog circuits. Nullors are pathological or singular elements that posses ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. Therefore, in order to compute symbolic expressions of pathological element-base equivalent analog circuits, the nullor properties should be taken into account in the formulation process. Nodal analysis (NA) of these circuits is very popular. However, the recently proposed methods of formulation the nodal admittance (NA) matrix, require many operations on the rows and columns of an initial node admittance matrix (INAM), which has the order (nxn), for the (n+1) node network or a laborious procedure of computation of norator and nullator indexes. This paper presents a new method of formulation of the nodal admittance matrix for linear active circuits with nullors that performs direct construction of the final nodal admittance matrix (FNAM), which has the order (n-k)x(n-k), and uses only classical methods of element stamps. (k is the number of nullators and norators pairs). The viability and the potentiality of the proposed method (of the FNAM) is showcased via application examples. The improved formulation method is compared with other formulation methods, showing that it is simpler.

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CADsEDA industry professionals, academics and students.

Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm

When ICCAD began in 1983, we had no robust tools for device modelling, analog circuit synthesis, electrical timing simulation, transistor-to-logic abstraction, or large-scale custom circuit tuning. Today, all these techniques are in common industrial usage, most commercially available. The seven papers in this section fundamentally transformed the way in which we model, manipulate, and solve these difficult tasks today. They are linked by a common thread of “deep circuits innovation”.

This paper describes CODAC, a CAD tool for characterization and analysis of analog and digital circuits. It is based primarily on the industry standard electrical simulator, SPICE. CODAC provides a powerful C like language for specifying the characterization problem. In addition to providing an extensive library of built-in analysis functions it also supports a procedural interface that facilitates the definition of customized analysis functions. A capability to distribute in parallel the large number of simulation runs for an extensive circuit analysis (e.g. Monte Carlo analysis) is provided which significantly reduces overall cycle time. CODAC is being successfully used for circuit analysis and as a part of analog and digital library development flow at Texas Instruments.

Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.

Finding critical nodes and devices inside a circuit is important to have a reliable and safe circuit. It is also a necessary information to successfully solve a failure analysis. Besides, this is a difficult task when dealing with analog and mixed signal circuits for safety applications. For complex designs, the list of signals that influences a selected output is not easy to be deduced. This paper proposes a solution to meet these needs. It is a method that is potentially opened to a broader application domain than failure analysis. The obtained results are encouraging and show the advantages of such approach.

In this paper, we describe the complete MOSFET model developed for circuit simulations. The model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. The unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. Additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model.

In this paper, we describe the complete MOSFET model developed for circuit simulations. The model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. The unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. Additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model.

Problem statement: Day by day more and more products rely on analog circuits to improve the speed and reduce the power consumption(Products rely on analog circuits to improve the speed and reduce the power consumption day by day more and more.). For the VLSI implementation analog circuit design plays an important role. This analog circuit synthesis might be the most challenging and time-consumed task, because it does not only consist of topology and layout synthesis but also of component sizing. Approach: A Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. Analog signal processing finds many applications and widely uses OpAmp based amplifiers, mixers, comparators. and filters. Results: A two-stage opamp (Miller Operational Trans-conductance Amplifier (OTA)) is considered for the synthesis that satisfies certain design specifications. Performance has been evaluated with the Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulator until optimal sizes of the transistors are found. Conclusion: The output of the simulation for the two-stage opamp shows that the PSO technique is an accurate and promising approach in determining the device sizes in an analog circuit.

From the Publisher: The analysis of nonlinear hybrid electromagnetic systems poses significant challenges that essentially demand reliable numerical methods. In recent years, research has shown that finite-difference time-domain (FDTD) cosimulation techniques hold great potential for future designs and analyses of electrical systems.Time-Domain Computer Analysis of Nonlinear Hybrid Systems summarizes and reviews more than 10 years of research in FDTD cosimulation. It first provides a basic overview of the electromagnetic theory, the link between field theory and circuit theory, transmission line theory, finite-difference approximation, and analog circuit simulation. The author then extends the basic theory of FDTD cosimulation to focus on techniques for time-domain field solving, analog circuit analysis, and integration of other lumped systems, such as n-port nonlinear circuits, into the field-solving scheme.The numerical cosimulation methods described in this book and proven in various applications can effectively simulate hybrid circuits that other techniques cannot. By incorporating recent, new, and previously unpublished results, this book effectively represents the state of the art in FDTD techniques. More detailed studies are needed before the methods described are fully developed, but the discussions in this book build a good foundation for their future perfection.

We describe a new extraction tool, EMX (Electro-Magnetic eXtractor), for the analysis of RF, analog and high-speed digital circuits. EMX is a fast full-wave field solver. It incorporates two new techniques which make it significantly faster and more memory-efficient than previous solvers. First, it takes advantage of layout regularity in typical designs. Second, EMX uses a new method for computing the vector-potential component in the mixed potential integral equation. These techniques give a speed-up of more than a factor of ten, together with a corresponding reduction in memory.

While the proliferation of electronics has been driven by computing and consumer applications for a long time, integrated circuits (ICs) presently undergo accelerated integration into healthcare, transportation, robotics, and autonomous systems. In addition to provision of prescribed functionalities of sensing, computing, and processing, these ICs must meet stringent reliability specifications in order to safeguard performance and safety of the whole mission-critical system where deployed. Circuits designed to be fail-safe by design exhibit low occurrences of failure. However, having a sign of no failure under typical verification and test procedures yields no guarantee for meeting a given near-zero or extremely-low failure specification. On the other hand, exhaustiveness may never be achieved by brute-force failure detection, which results in an unacceptably high cost in simulation and testing. This project will develop efficient machine-learning techniques for extremely-rare circuit-failure detection without needing large amounts of expensive simulation or test data. The proposed techniques will enable cost-effective verification and test of reliability-critical ICs and mission-critical systems in general. The research undertaken will also enable the two groups at UC Santa Barbara and UT Dallas to educate and train undergraduate and graduate students, including women and underrepresented groups, thus expanding the and contributing to the much needed US technological workforce. It is believed that extracting critical failure information via machine learning within practical limits of available measurement or simulation data can go a long way towards extremely rare failure detection. This project centers on developing an active-learning framework that intelligently samples in the high-dimensional space of complex interacting design parameters, manufacturing variations, and operating conditions, achieving the goal of data-efficient detection of rare circuit failures. The targeted active-learning framework will be supported by the development of machine-learning model foundations and robust learning methods that can scale to high-dimensional parameter spaces. The key objective of this project is to make extremely-rare failure discovery and identification of the underlying failure mechanisms practically viable by extracting the maximum amount of useful information possible from a small amount of available data. The proposed extremely-rare failure discovery work will be broadly applicable to verification and failure analysis of analog, mixed-signal, radio-frequency, and memory circuits with stringent failure specifications and many other types of mission-critical systems. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. https://underline.io/speakers/59522-hanbin-hu

This chapter gives a description of the extension of Generalized Parameter Extraction Method (GPEM) for symbolic analysis of large-scale analog circuits containing pathological elements. The brief overview of the parameter extraction approach is included. An algorithm implementing the concept of Higher Order Summative Cofactors (HOSC) for determinants computation of the pathological element-based circuits is proposed. In this chapter, we also present the hierarchical decomposition techniques of upward and downward analysis of electronic circuits by GPEM. The proposed techniques are used in freeware symbolic analyzer CirSym. Several examples are presented to illustrate the advantages of the GPEM applications.

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.