Generalized Parameter Extraction Method for Symbolic Analysis of Analog Circuits Containing Pathological Elements

Symbolic circuit analysis using Mathematics A method of symbolic circuit analysis using Mathematica is reported. With the powerful symbolic manipulation capacity of Mathematica, symbolic circuit analysis is significantly simplified. The analysed circuits can be passive or active, with active devices modelled by nullors. Non-trivial circuit analysis examples are presented and the program list is given.

Parallel to algebraic methods, graphical circuit analysis methods have the advantage of cancellation-free. This paper proposes a graph reduction method for hierarchical symbolic circuit analysis by applying a binary decision diagram (BDD) for data sharing. This method is extended from the Graph-Pair Decision Diagram (GPDD) method which was developed for two-port dependent sources. New graph construction rules for multiple-port dependent sources are introduced, with which large analog circuits can be analyzed hierarchically. The new hierarchical method guarantees the cancellation-free property at each layer of hierarchy. The BDD-based hierarchical analysis method can greatly reduce the analysis complexity of the entire circuit, while the software construction and circuit partition remain easy. The new method is compared to the algebraic hierarchical method based on DDD (Determinant Decision Diagram) which does not have the cancellation-free property. Comparable performance can be achieved with the new method which has the extra cancellation-free property.

The general framework of a symbolic analysis environment for linear time-invariant circuits is presented. Such a framework consists of two major parts: a simplification at circuit level and a simplifying expression-generation. An overview of the known techniques for both circuit simplification and expression generation is given, and in addition a new nonhierarchical expression generation technique based on the concept of determinant decision diagrams (DDDs) is presented. The DDD-based technique is evaluated on a set of benchmark circuits together with a known fast symbolic analysis algorithm, and turns out to be the most efficient. The DDD-based expression generation algorithm is, therefore, the best solution for nonhierarchical linear symbolic expression generation to the authors' knowledge.

The nullor, as a network element, is very popular in the areas of modeling, synthesis and analysis of analog circuits. Nullors are pathological or singular elements that posses ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. Therefore, in order to compute symbolic expressions of pathological element-base equivalent analog circuits, the nullor properties should be taken into account in the formulation process. Nodal analysis (NA) of these circuits is very popular. However, the recently proposed methods of formulation the nodal admittance (NA) matrix, require many operations on the rows and columns of an initial node admittance matrix (INAM), which has the order (nxn), for the (n+1) node network or a laborious procedure of computation of norator and nullator indexes. This paper presents a new method of formulation of the nodal admittance matrix for linear active circuits with nullors that performs direct construction of the final nodal admittance matrix (FNAM), which has the order (n-k)x(n-k), and uses only classical methods of element stamps. (k is the number of nullators and norators pairs). The viability and the potentiality of the proposed method (of the FNAM) is showcased via application examples. The improved formulation method is compared with other formulation methods, showing that it is simpler.

A hierarchical symbolic analyzer (SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we propose a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit, which detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed binary decision diagrams (ZBDDs). ZBDDs are essentially determinant decision diagrams (DDDs) representation of a determinant. The significance of the new method is that all product terms can be constructed implicitly and simultaneously, in contrast to all previous symbolic analysis methods where symbolic terms are generated explicitly and sequentially by Laplace expansion or topological methods. We further apply the logic synthesis idea to generating symbolic coefficients of s-expanded polynomials and present a method to compute coefficients individually and selectively. Our new approach demonstrates an inherent relationship between circuit simulation and logic synthesis for the first time. Experimental results show the speedup of our new method over the existing flat method and its greater capacity over both existing flat and hierarchical symbolic analyzers.

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of a core embedded deep in the circuit and propagating test responses from the core outputs. In this paper, we first present a design for testability technique for testing such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transparent so that they can propagate test data without information loss. This testability and transparency technique is currently applicable to cores of the following types: application-specific integrated circuits, application-specific programmable processors, and application-specific instruction processors. Other core types can be made testable and transparent using traditional techniques. The testable and transparent cores can then he integrated together with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to the core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierarchical testability analysis method that has been successfully applied to register-transfer level circuits. Since the testability analysis method is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a byproduct of the testability analysis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated: (1) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan and (2) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

A prototype system to aid analog design engineers in the synthesis and analysis of CMOS analog circuits has been developed. ACAD (analog computer-aided design) differs from other tools by its extensive use of hierarchy and two-port network theory to subdivide the process of solving the small signal network functions. This allows larger circuits to be analyzed. ACAD solved and simplified all of the two-port network equations for an operational amplifier containing 29 MOS transistors, 2 resistors, and 3 capacitors by analyzing, simplifying, and combining four subcircuits. ACAD produced the correct results for the model being evaluated. These results show that computer-aided hierarchical small signal model analysis of analog circuits is possible.

Frances E. Dolan, Marriage and Violence: The Early Modern LegacyMarriage and Violence: The Early Modern Legacy. Frances E. Dolan. Philadelphia: University of Pennsylvania Press, 2008. Pp. 235.

SummaryRecently, abstract current mirror and voltage mirror elements have been proposed for behavioral modeling of active analog blocks. Such artificial elements and the traditionally used nullor element together are called pathological elements in the literature. Pathological elements are very useful in modeling and analysis of active network. Hence, researchers have been motivated to study symbolic analysis methods for networks containing pathological elements. However, so far, only nodal admittance matrix analysis has been formulated. In this work, an alternative two‐graph method is formulated, which has the advantage of providing a compact intermediate form for subsequent symbolic term generation. With a compact two‐graph representation, either a matrix method or a tree enumeration method can be employed. For completeness, the classical two‐graph theory has been extended in this paper to encompass all four types of dependent sources and all pathological elements. Illustrative examples are presented to demonstrate the principle of compact symbolic term generation by the presented two‐graph method. Copyright © 2014 John Wiley &amp; Sons, Ltd.

We propose a novel method of symbolic time-series analysis aimed at characterizing the regular or chaotic dynamics of coupled oscillators. The method is applied to two identical pendulums mounted on a frictionless platform, resembling Huygens’ clocks. Employing a transformation rule inspired in ordinal analysis [C. Bandt and B. Pompe, Phys. Rev. Lett. 88, 174102 (2002)], the dynamics of the coupled system is represented by a sequence of symbols that are determined by the order in which the trajectory of each pendulum intersects an appropriately chosen hyperplane in the phase space. For two coupled pendulums we use four symbols corresponding to the crossings of the vertical axis (at the bottom equilibrium point), either clock-wise or anti-clock wise. The complexity of the motion, quantified in terms of the entropy of the symbolic sequence, is compared with the degree of chaos, quantified in terms of the largest Lyapunov exponent. We demonstrate that the symbolic entropy sheds light into the large variety of different periodic and chaotic motions, with different types synchronization, that cannot be inferred from the Lyapunov analysis.

This work proposes canonical constrained narrowing, a new symbolic reachability analysis technique applicable to topmost rewrite theories where the equational theory has the finite variant property. Our experiments suggest that canonical constrained narrowing is more efficient than both standard narrowing and the previously studied contextual narrowing. These results are relevant not only for Maude-NPA, but also for symbolically analyzing many other concurrent systems specified by means of rewrite theories.

In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonov's functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis method. The new algorithm can give transient lower bound and upper bound of the performance variations affected analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method.

The generalization of Bode’s sensitivity analysis technique for all types of the transfer functions and circuit elements is presented in the paper. The proposed formulae for first- and second-order symbolic sensitivity calculation provide the compact size of obtained expression and have the advantages of cancellation-free sum-of-product terms and matrix-free computation. This is achieved by means of the concept of high order summative cofactors and the generalized parameter extraction method. The proposed technique is implemented in symbolic circuit analysis program Cirsym. Illustrative example on symbolic sensitivity circuit analysis and comparison of the presented technique with the transimpedance method and the method based on the modified Coates flow-graph are given.

A new approach to the problem of symbolic circuit analysis of large-scale circuits is presented. The methodology has been implemented in a computer program called SCAPP (symbolic circuit analysis program with partitioning). The method solves the problem by utilizing a hierarchical network approach and the sequence of expressions concept rather than a topological approach and the single expression idea which have dominated symbolic analysis in the past. The result is a linear growth in the number of terms in the symbolic solutions for the network approach versus the exponential growth exhibited by traditional methods. The analysis methodology introduces the concept of the RMNA (reduced modified nodal analysis) matrix. This allows the characterization of symbolic networks in terms of only a small subset of the network variables (external variables) rather than the complete set of variables. The analysis algorithm is most efficient when network partitioning is used. Partitioning results in a reduction in the number of terms in the symbolic solutions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>