Research on high-performance remote sensing image real-time processing system

To produce different levels of spaceborne SAR imagery product, a real-time/near real-time signal processing system is discussed. Based on analysis of optimization of SAR signal processing algorithm, especially in CS imaging and normal geometric correction for level 1-2 product, the implementation of these algorithms on specific hardware is elaborated. The structure and design of the entire system provide great flexibility and high performance. Finally, some experiments and tests have been carried out to verify the feasibility of the system in high-resolution SAR signal processing.

Time is the best important resource in real-time video image processing system. Only few structure or algorithm can be used in real-time video image processing system because of time limitation. Establish a high speed data-access is a way to this problem. It transfer the video signal between output ports and kernel processor as less time delay. The mode, look-up-table, other analysis, adjustment or calculation rule will be applied first by medium or low data-access. We can choose different data-access according to data relation level. Data which has closer correlation will be treated through low-speed-access, which has loser correlation will be treated through medium-speed-access. Theory analysis and experiment showed that it is a high effective structure for real-time video image processing. The feature of video image and real-time processing system is presented in this paper. The basic theory of data-access is introduced also. The status and relation of high, medium, low data-access is discussed and the rules of data distribution in different access is analyzed. Some examples with datas-accesses are given in the paper (TV tracking and measuring, laser signal alarming system).

This paper presents the principle of synthetic aperture radar (SAR) imaging and points out that the SAR image can be achieved by two-dimensional convolution. Then, the system configuration of an airborne SAR real-time digital signal processing system and the logical structure of range and azimuth compression are described in detail. Finally the main performance parameters are analysed briefly and the results of a real-time test and examples of imagery obtained by the system are also presented.

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers; the conceptual and architectural models of RTOS+ is described in this paper, while the static and dynamic behavioral models of RTOS+ will be elaborated in a forthcoming paper.

This paper presents a real-time digital signal processing system to detect the presence of pedestrians waiting to cross an intersection. A pedestrian detection algorithm is developed and implemented on a TMS320C40 DSP chip such that videosignals captured and transmitted from an actual intersection are processed in real-time. The detection algorithm consists of a background update and a background subtraction components applied to image blocks. The background update is done in order to cope with brightness changes that occur in actual outdoor scenes.In addition, waiting and moving pedestrians are distinguished by using the temporal changes of image block intensities. The results obtained indicate that this DSP implementation provides an acceptable detection rate for this traffic management problem.

Emerging trends in design of real-time digital signal processing systems indicate that in the future, a significant amount of performance improvement can be achieved using dynamically reconfigurable embedded architectures consisting of reconfigurable, general-purpose components. Although embedded real-time systems have long been prevailing in our society, no firm scientific base has been established yet to handle timing requirements in a systematic manner in real-time embedded computing. Because of this lack of the scientific base, many embedded systems have been designed in an ad hoc manner and most of them have been customized to specific applications, showing inflexibility for the other type of applications. This paper proposes a dynamically reconfigurable embedded architecture which bridges the gap between the embedded system and ASICs. This architecture combines a reconfigurable hardware processing unit with a software programmable processor. The main goal is to take advantage of the capabilities of both resources. While the processor takes care of all sequential computations the reconfigurable hardware takes specialized vector operations. With such integrated system architecture, specific properties of applications, such as parallelism, regularity of computation and data granularity can be exploited by creating custom operators, pipelines and interconnection pathways. To handle the conflicting requirements of being a flexible architecture and implement some application-specific algorithms, a dynamically reconfigurable embedded architecture is proposed. The proposed architecture consists of arithmetic operation-level configurable modules interconnected through multiple data buses that can be logically configured to form one or more pipelines before a specific application is initiated and remains unchanged till the completion of the application. This architecture is targeted at high throughput and real time signal processing applications. The idea of dynamic reconfiguration - changing a circuit while it is operating - is exploited. In particular, we illustrate how dynamic reconfiguration can achieve significant performance improvement.

To clearly observe the upper urinary tract with a thin flexible endoscope, we developed a novel real-time image processing system. The dark cladding portion in an image guide was electrically painted out by the light which was emitted from each core pixels to obtain bright image. Thirty patients were examined using a thin flexible endoscope with this system at retrograde pyelography or puncture of a renal or prostatic cyst. The endoscope which was 0.75mm in diameter had 3,000 pixels of image fiber. The objectives were clearly seen without the dilation of the ureteral orifice. Finer and more colorful image could be obtained with this system. However, visualization was not clear in 4 patients because of poor manipulation capability at the endoscope tip. There were no complications, such as perforation of the ureter. We concluded that a thin endoscope with the real-time processing system would be useful for the diagnosis or treatment of the upper urinary tract or a cystic disease.

In order to meet the tomato color sorting system with the requirements of multi-channel data acquisition and real-time processing, [ ]firstly, a multi-channel color digital acquisition and processing technique program based on FPGA were proposed . Then, a multi-channel data acquisition and real-time parallel processing system was built. The RGB color sensors were slected as detection components and the FPGA chip EP1C3T144C8 was slected as a core of data acquisition and processing. Meanwhile, ports of signal acquisition and the solenoid valve control were adopted a two-way analog switch HC4051 for saving I/O ports of FPGA. Thirdly, under the modular design and module reuse principles, we developed all modules with VHDL Language in QuartusII development environment. Finally, RTL and time sequence simulation for the system were done. The results showed that the connections between the modules accord with control logics. [²»´o¶O accorded ¹ýE¥E½] The performance of system time sequencev are good, which can meet with the requirements of real-time processing of tomato color sorting. On these bases, we also conducted a tomato sorting test verification. The results showed that the average accuracy of sorting is 98.70% and coefficient of variation is 0.01. This results can meet requirements of production.

The Ingara airborne imaging radar system is a technology demonstrator aimed at evaluating the application of multi-mode radar to broad area land surveillance. An integrated system has been developed that includes an X-Band radar with SAR and MTI modes, real-time signal processing system, air-to-ground data link, automated target detection algorithms and a simple image analysis geographical information system.

Data compression techniques have been widely used to process and transmit huge amount of EEG data in real-time and remote EEG signal processing systems. In this paper we propose a lossy compression technique, F-shift, to compress EEG signals for remote depth of Anaesthesia (DoA) monitoring. Compared with traditional wavelet compression techniques, our method not only preserves valuable clinical information with high compression ratios, but also reduces high frequency noises in EEG signals. Moreover, our method has negligible compression overheads (less than 0.1 seconds), which can greatly benefit real-time EEG signal monitoring systems. Our extensive experiments demonstrate the efficiency and effectiveness of the proposed compression method.

With the wide-spread using of LinuxOS, the Real-time requirement in certain applications is heighly demanded. So the Xenomai comes up, it has a higher priority than Linux kernel, so it can deal with the tasks which need real-time requirement.In order to set up the real-time Linux based on the ARM platform, the mini2440 development board contained s3c2440 as its MCU is used to set up the real-time operation system. Design and test the performs of the system. The results show that the embeded real-time Linux system based on the Xenomai has the good quality of real-time and can be used in the soft real-time system or the hard real-time system.

This paper addresses the problem of deriving optimised array architectures for real-time multi-dimensional signal processing systems, as occurring in image, speech and video applications. The starting point is a set of Weak Single Assignment Codes. For this abstract specification, we solve the difficult task of finding a globally optimised architecture with matched throughput while avoiding an explosion of the search space. The cost function not only includes the data-path area but incorporates also the crucial foreground and background memory storage. The effectiveness of our solution has been substantiated with realistic test cases. >

The design and use of two new inductive sensors for imaging of reinforcing bars in concrete is described. The first is a Q-sensor, the second a heterodyne sensor. By exploiting the phase and amplitude of the returned signals, it is possible to image the steel bars, detect section loss due to corrosion and image corrosion products directly. A real-time time digital signal processing system has also been developed that performs data pre-processing.

Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.

The purpose of this study is to help reduce high noise levels experienced by patients in intensive care unit (ICU) environments. The study has designed and developed the active noise control (ANC) system based on filtered x least mean square (FxLMS) to reduce the interfering noise around ICU patients’ beds. A multi-channel feed-forward ANC algorithm has been implemented in a real-time digital signal processing system based on TMS320 DSP C6713. This noise cancellation system has been tested in a patient bed with recorded real ICU noise as the noise source to mimic the ICU noisy environment. The experiment setup has been presented. The real-time experiment results show that ANC is a promising solution to solve high noise level problem inside ICU.