Resource-constrained pipelining based on loop transformations

With increasing demands for performance by embedded systems, especially by digital signal processing (DSP) applications, embedded processors must increase available instructionlevel parallelism (ILP) within significant constraints on power consumption and chip cost. Unfortunately, supporting a large amount of ILP on a processor while maintaining a single register file increases chip cost and potentially decreases overall performance due to increased cycle time. To address this problem, some modern embedded processors partition the register file into multiple low-ported register files, each directly connected with one or more functional units. These functional unit/register file groups are called clusters. Clustered VLIW (very long instruction word) architectures need extra copy operations or delays to transfer values among clusters. To take advantage of clustered architectures, the compiler must expose parallelism for maximal functional-unit utilization, and schedule instructions to reduce intercluster communication overhead. High-level loop transformations offer an excellent opportunity to enhance the abilities of low-level optimizers to generate code for clustered architectures. This dissertation investigates the effects of three loop transformations, i.e., loop fusion, loop unrolling, and unroll-and-jam, on clustered VLIW architectures. The objective is to achieve high performance with low communication overhead. This dissertation discusses the following techniques: Loop Fusion This research examines the impact of loop fusion on clustered architectures. A metric based upon communication costs for guiding loop fusion is developed and tested on DSP benchmarks. Unroll-and-jam and Loop Unrolling A new method that integrates a communication cost model with an integer-optimization problem is developed to determine unroll amounts for loop unrolling and unroll-and-jam automatically for a specific loop on a specific architecture. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures.

In the area of Embedded Systems, instruction memories are one of the critical components consuming significant amounts of energy. Existence of a relation between size of the compiled program, and consequently required size of the instruction memory, and the compiler optimization flags is well-known. In particular, loop transformations such as loop unrolling, while having potential to increase performance dramatically, often cause unreasonable growth in the size of the required instruction memory, causing loss of benefit of lower cycle count from overall system energy point of view. One method how to decrease energy consumption of the memories is use of instruction buffers. Often executed loops are stored in the buffer and executed from there, while main memory is not read. In this paper, we show how the compiler flag, controlling loop unrolling, influences the structure of the loops in the program. While unrolling improves performance, unrolled loops can disappear from the program completely, or grow to unreasonable size where use of instruction buffer brings no benefits from the energy point of view.

Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using speculative code motions and loop transformations, generates a finite state machine for the scheduled design graph, and then finally outputs a synthesizable RTL VHDL code. To handle loop algorithm, SPARK employs various loop transformations such as loop invariant code motion, loop unrolling, loop index variable elimination and loop shifting. In loop synthesis, however, SPARK does not produce circuit description whose quality can compete with manual designs. With the objective of improving the quality of high-level synthesis results for designs with loops, this paper shows an upgrade of SPARK through transforming nested loops into a 2-D systolic array to increase parallelism. The C-to-VHDL loop synthesis in this paper achieves synthesis results that are better than those achieved from a current version of SPARK for matrix-matrix multiplication and FIR filter, and can be incorporated into SPARK parallelizing high-level synthesis framework.KeywordsNest LoopSystolic ArrayTotal Execution TimeHardware ComplexitySynthesis ResultThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Directives for the compiler such as pragmas can help programmers to separate an algorithm's semantics from its optimization. This keeps the code understandable and easier to optimize for different platforms. Simple transformations such as loop unrolling are already implemented in most mainstream compilers. We recently submitted a proposal to add generalized loop transformations to the OpenMP standard. We are also working on an implementation in LLVM/Clang/Polly to show its feasibility and usefulness. The current prototype allows applying patterns common to matrix-matrix multiplication optimizations.

The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8- mu m BiCMOS technology, are described. The technology improvements associated with the three most recent microprocessor generations are outlined. The Pentium's compatibility, performance, organization, and development process are also described. The compiler technology developed with the Pentium microprocessor, which includes machine-independent optimizations common to current high-performance compilers, such as inlining, unrolling, and other loop transformations, is reviewed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The current practice of mapping computations to custom hardware implementations requires programmers to assume the role of hardware designers. In tuning the performance of their hardware implementation, designers manually apply loop transformations such as loop unrolling. designers manually apply loop transformations. For example, loop unrolling is used to expose instruction-level parallelism at the expense of more hardware resources for concurrent operator evaluation. Because unrolling also increases the amount of data a computation requires, too much unrolling can lead to a memory bound implementation where resources are idle. To negotiate inherent hardware space-time trade-offs, designers must engage in an iterative refinement cycle, at each step manually applying transformations and evaluating their impact. This process is not only error-prone and tedious but also prohibitively expensive given the large search spaces and with long synthesis times. This paper describes an automated approach to hardware design space exploration, through a collaboration between parallelizing compiler technology and high-level synthesis tools. We present a compiler algorithm that automatically explores the large design spaces resulting from the application of several program transformations commonly used in application-specific hardware designs. Our approach uses synthesis estimation techniques to quantitatively evaluate alternate designs for a loop nest computation. We have implemented this design space exploration algorithm in the context of a compilation and synthesis system called DEFACTO, and present results of this implementation on five multimedia kernels. Our algorithm derives an implementation that closely matches the performance of the fastest design in the design space, and among implementations with comparable performance, selects the smallest design. We search on average only 0.3% of the design space. This technology thus significantly raises the level of abstraction for hardware design and explores a design space much larger than is feasible for a human designer.

Customer order acceptance is an important process in make-to-order industries. Acceptance policies should operate such that a pre-specified delivery reliability is achieved, while maximizing resource utilization. By selecting orders with specific characteristics that maximize resource utilization, an important and often unforeseen effect occurs: the mix of orders changes such that the expected delivery reliability is no longer met. This paper investigates the selectivity of an aggregate and a detailed acceptance procedure, for batch process industries featuring complex job and resource structures. We found that the detailed policy maximizes resource utilization but underestimates the consequences on the realized makespan of significantly changing the job mix. The aggregate policy, while being selective, performs much better with respect to the delivery reliability, but achieves a lower capacity utilization. We propose a third procedure, the hybrid policy, which combines the strengths of both the detailed and aggregate acceptance procedures. Simulation experiments show that the hybrid policy successfully controls the delivery reliability, without loosing much of the beneficial effect of the selectivity on utilization.

The purpose of this article is to emphasize on client interaction techniques and practices with regard to the hotel's location, design, and personalized services. By addressing this knowledge gap, it is expected that the study will support the appropriate use of hotel resources, including internal design practices, hotel location offerings and practices, customer promotional practices, personalized service practices, and art and cultural practices. In the end, this engages a client and results in their intention to repurchase the services.The qualitative approach based on thematic analysis is used in this study. Hotel managers and executives were interviewed in-depth. The final transcript for analysis was created by transcribing the audio recordings of the interviews. As a result, a pertinent list of themes and actions has been created by coding the reported customer engagement practices. The factors like hotel’s location, hotel’s design and personalized services offered by the hotels taken into consideration for this study, adds to the list of customer engagement practices. Hotel internal design practices, location offerings/practices, Customer-oriented practices, Personalized service practices, customer promotional practices, Art and Cultural Practices from data reporting and was identified to be used by hotel establishments to enhance their customer satisfaction and repurchase intention. The kind of factors like hotel location, hotel design, and personalized services offered by the hotel taken into consideration for this study helps to identify more customer engagement practices. The identified practices also act as a guide for the hotel operators so that maximum utilization of resources can be ensured in terms of accessibility and availability with respect to hotel location, hotel design, and personalized service offered by the hotel. Hotels must also have a complete mechanism for learning and development of service personnel so that they can anticipate the needs of the guest and offer personalized services. It is anticipated that by filling this knowledge gap, the study will assist in proper utilization of resources available with a hotel in the form of hotel internal design practices, hotel location offerings/practices, customer promotional practices, personalized service practices, and art and cultural practices. This approach engages a customer and leads to the repurchase intention of services.

The rapid progress of cloud-edge collaborative computing poses significant challenges for existing approaches, as they struggle to simultaneously satisfy the diverse timing requirements of multiple workflows and minimize resource execution costs during dynamic scheduling and concurrent workflow execution. This presents a significant challenge in reducing the execution costs of various workflow applications within deadline constraints. Therefore, an enhanced butterfly optimization algorithm (SBOA) is proposed, which balances exploration and exploitation of the solution space by modeling the butterfly's foraging behavior based on scent concentration and introducing a priority-based dynamic initialization strategy. Additionally, a dual-objective optimization model is developed to dynamically optimize both execution cost minimization and resource utilization maximization by transforming the execution costs and resource utilization of multiple workflow applications into quantifiable scheduling objectives. Experiments conducted on real-world datasets such as Montage and CyberShake demonstrate that SBOA achieves an average improvement of 30.00% in resource utilization and an average reduction of 52.13% in execution cost compared to the baseline algorithm. These results validate the effectiveness of SBOA in minimizing costs and maximizing resource utilization under complex constraints.

Cloud load balancing is done to persist the services in the cloud environment along with quality of service (QoS) parameters. An efficient load balancing algorithm should be based on better optimization of these QoS parameters which results in efficient scheduling. Most of the load balancing algorithms which exist consider response time or resource utilization constraints but an efficient algorithm must consider both perspectives from the user side and cloud service provider side. This article presents a load balancing strategy that efficiently allocates tasks to virtualized resources to get maximum resource utilization in minimum response time. The proposed approach, join minimum loaded queue (JMLQ), is based on the existing join idle queue (JIQ) model that has been modified by replacing idle servers in the I-queues with servers having one task in execution list. The results of simulation in CloudSim verify that the proposed approach efficiently maximizes resource utilization by reducing the response time in comparison to its other variants.

This paper presents a hybrid approach based discrete Particle Swarm Optimization (PSO) and chaotic strategies for solving multi-objective task scheduling problem in cloud computing. The main purpose is to allocate the summited tasks to the available resources in the cloud environment with minimum makespan (i.e. schedule length) and processing cost while maximizing resource utilization without violating Service Level Agreement (SLA) among users and cloud providers. The main challenges faced by Particle Swarm Optimization (PSO) when used to solve scheduling problems are premature convergence and trapping into local optimum. This paper presents an enhanced Particle Swarm Optimization algorithm hybridized with Chaotic Map strategies. The proposed approach is called Enhanced Particle Swarm Optimization based Chaotic Strategies (EPSOCHO) algorithm. Our proposed approach suggests two Chaotic Map strategies: sinusoidal iterator and Lorenz attractor to enhanced PSO algorithm in order to get good convergence and diversity for optimizing the task scheduling in cloud computing. The proposed approach is simulated and implemented in Cloudsim simulator. The performance of the proposed approach is compared with the standard PSO algorithm, the improved PSO algorithm with Longest job to fastest processor (LJFP-PSO), and the improved PSO algorithm with minimum completion time (MCT-PSO) using different sizes of tasks and various benchmark datasets. The results clearly demonstrate the efficiency of the proposed approach in terms of makespan, processing cost and resources utilization.

Software Defined Networking (SDN) and Network Function Virtualization (NFV) are transforming Data Center (DC), Telecom, and enterprise networking. The programmability offered by P4 enables SDN to be more protocol-independent and flexible. Data Centers are increasingly adopting SmartNICs (sNICs) to accelerate packet processing that can be leveraged to support packet processing pipelines and custom Network Functions (NFs). However, there are several challenges in integrating and deploying P4 based SDN control as well as host and sNIC-based programmable NFs. These include configuration and management of the data plane components (Host and sNIC P4 switches) for the SDN control plane and effective utilization of data plane resources. P4NFV addresses these concerns and provides a unified P4 switch abstraction framework to simplify the SDN control plane, reducing management complexities, and leveraging a host-local SDN Agent to improve the overall resource utilization. The SDN agent considers the network-wide, host, and sNIC specific capabilities and constraints. Based on workload and traffic characteristics, P4NFV determines the partitioning of the P4 tables and optimal placement of NFs (P4 actions) to minimize the overall delay and maximize resource utilization. P4NFV uses Mixed Integer Linear Programming (MILP) based optimization formulation and achieves up to 2. 5X increase in system capacity while minimizing the delay experienced by flows. P4NFV considers the number of packet exchanges, flow size, and state dependency to minimize the delay imposed by data transmission over PCI Express interface.

Telemedicine in the intensive care unit (tele-ICU) is an increasingly significant field that leverages advanced technology to provide remote critical care services for patients in the ICU. The primary goal of tele-ICU is to enhance access to expert intensive care specialists, improve clinical outcomes, and optimize the management of critical care capacity and resources. Numerous studies have demonstrated that telemedicine can improve the efficiency of resource utilization, foster adherence to clinical best practices, and directly enhance both the quality of care and patient outcomes in the ICU setting. Moreover, telemedicine facilitates greater access to critical care knowledge, strengthens collaboration between healthcare providers across different institutions, and supports the development of specialized training programs for critical care professionals. Currently, the most widely adopted tele-ICU model is the centralized hub-and-spoke model, where a central monitoring station oversees multiple ICUs at geographically distant locations. While this model has proven effective in many contexts, there remains significant potential for further advancements in tele-ICU practices. In this article, we propose two novel theoretical models of tele-ICU that aim to address current limitations, improve quality of care, optimize personnel deployment, and maximize resource utilization. These proposed models are intended to offer a more flexible, scalable, and efficient approach to delivering critical care in diverse healthcare settings, ultimately contributing to better patient outcomes and more sustainable healthcare practices.

Server virtualization is a powerful strategy for optimizing network infrastructure. It allows multiple virtual servers to run on a single physical server, maximizing resource utilization and improving efficiency. Deploying server virtualization using Docker technology offers a lightweight and flexible approach to optimizing network infrastructure. Docker contains package applications and their dependencies, enabling consistent and efficient deployment across various environments. Specifically, optimizing virtual server infrastructure using Docker Technology in the automotive sector focuses on improving the efficiency and management of the company's virtual server resources. By implementing Docker technology, a container platform that allows the packaging and running of applications in a lightweight and secure manner, the project aims to reduce operational costs and increase the agility and scalability of IT services. Adopting Docker will facilitate the rapid deployment of applications, ensuring a consistent and isolated execution environment for each one. This will allow the company to manage its workloads more efficiently and respond quickly to market needs, reassuring the audience about the potential improvements in their work processes. The study is developed under the top-down methodology guidelines for the design of telematics systems. It also includes a detailed analysis of the current server performance, a proposal for restructuring the existing infrastructure, and a plan to implement DevOps practices to optimize development and operational processes. With these changes, a significant improvement in system availability and performance is expected, thus contributing to the company's growth and technological innovation. The benefits of Docker implementation are numerous, including lightweight (containers share the host OS kernel, reducing overhead), portability (consistent environment across development, testing, and production), scalability (effortlessly scale containers horizontally), isolation (each container runs in its isolated environment), and efficiency (optimal resource utilization compared to traditional VMs). These benefits promise a brighter future for the company's IT infrastructure.

This paper presents an adaptive fault-tolerant resource allocation protocol tailored for FlyNet, a dynamic aerial network characterized by its mobility and three-dimensional operational space. Addressing the challenges of network partitioning and resource allocation in aerial networks, the proposed algorithm dynamically adjusts to the network's changing topology, ensuring consistent and efficient resource management. Through robust fault tolerance mechanisms, the protocol enhances FlyNet's reliability, maintaining seamless communication and optimal resource utilization even amid node mobility and disruptions. Simulation results demonstrate the algorithm's effectiveness in adapting to dynamic environments, maximizing resource utilization, and minimizing communication delays.