High-Level Synthesis Using SPARK and Systolic Array

: Many of today's high-performance computer processors are super-scalar. They can dispatch multiple instructions per cycle and, hence, provide what is commonly referred to as instruction-level parallelism. This super-scalar capability, combined with software pipelining, can increase processor throughput dramatically. Achieving maximum throughput, however, is nontrivial. Compilers must engage in aggressive optimization techniques, such as loop unrolling, speculative code motion, etc., to structure code to take full advantage of the underlying computer architecture. The phase-ordering implications of these optimizations are not well understood and are the subject of continuing research. Of particular interest are optimizations that enhance instruction-level parallelism. Two of these are loop unrolling and loop fusion. These are source-level optimizations that can be performed by either the programmer or the compiler. These optimizations have dramatic effects on the compiler's instruction scheduler. Performed too aggressively, these optimizations can increase register pressure and result in costly memory references. This paper details experiments performed to measure the effects of these source-level code transformations and how they influenced register pressure and code performance.

With increasing demands for performance by embedded systems, especially by digital signal processing (DSP) applications, embedded processors must increase available instructionlevel parallelism (ILP) within significant constraints on power consumption and chip cost. Unfortunately, supporting a large amount of ILP on a processor while maintaining a single register file increases chip cost and potentially decreases overall performance due to increased cycle time. To address this problem, some modern embedded processors partition the register file into multiple low-ported register files, each directly connected with one or more functional units. These functional unit/register file groups are called clusters. Clustered VLIW (very long instruction word) architectures need extra copy operations or delays to transfer values among clusters. To take advantage of clustered architectures, the compiler must expose parallelism for maximal functional-unit utilization, and schedule instructions to reduce intercluster communication overhead. High-level loop transformations offer an excellent opportunity to enhance the abilities of low-level optimizers to generate code for clustered architectures. This dissertation investigates the effects of three loop transformations, i.e., loop fusion, loop unrolling, and unroll-and-jam, on clustered VLIW architectures. The objective is to achieve high performance with low communication overhead. This dissertation discusses the following techniques: Loop Fusion This research examines the impact of loop fusion on clustered architectures. A metric based upon communication costs for guiding loop fusion is developed and tested on DSP benchmarks. Unroll-and-jam and Loop Unrolling A new method that integrates a communication cost model with an integer-optimization problem is developed to determine unroll amounts for loop unrolling and unroll-and-jam automatically for a specific loop on a specific architecture. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures.

In the area of Embedded Systems, instruction memories are one of the critical components consuming significant amounts of energy. Existence of a relation between size of the compiled program, and consequently required size of the instruction memory, and the compiler optimization flags is well-known. In particular, loop transformations such as loop unrolling, while having potential to increase performance dramatically, often cause unreasonable growth in the size of the required instruction memory, causing loss of benefit of lower cycle count from overall system energy point of view. One method how to decrease energy consumption of the memories is use of instruction buffers. Often executed loops are stored in the buffer and executed from there, while main memory is not read. In this paper, we show how the compiler flag, controlling loop unrolling, influences the structure of the loops in the program. While unrolling improves performance, unrolled loops can disappear from the program completely, or grow to unreasonable size where use of instruction buffer brings no benefits from the energy point of view.

Resource-constrained pipelining based on loop transformations

Directives for the compiler such as pragmas can help programmers to separate an algorithm's semantics from its optimization. This keeps the code understandable and easier to optimize for different platforms. Simple transformations such as loop unrolling are already implemented in most mainstream compilers. We recently submitted a proposal to add generalized loop transformations to the OpenMP standard. We are also working on an implementation in LLVM/Clang/Polly to show its feasibility and usefulness. The current prototype allows applying patterns common to matrix-matrix multiplication optimizations.

Designs generated by high-level synthesis (HLS) tools typically achieve a lower frequency compared to manual RTL designs. In this work, we study the timing issues in a diverse set of realistic and complex FPGA HLS designs. (1) We observe that in almost all cases the frequency degradation is caused by the broadcast structures generated by the HLS compiler. (2) We classify three major types of broadcasts in HLS-generated designs, including high-fanout data signals, pipeline flow control signals and synchronization signals for concurrent modules. (3) We reveal a number of limitations of the current HLS tools that result in those broadcast-related timing issues. (4) We propose a set of effective yet easy-to-implement approaches, including broadcast-aware scheduling, synchronization pruning, and skid-buffer-based flow control. Our experimental results show that our methods can improve the maximum frequency of a set of nine representative HLS benchmarks by 53% on average. In some cases, the frequency gain is more than 100 MHz.

Partial Redundancy Elimination (PRE) is a general scheme for suppressing partial redundancies which encompasses traditional optimizations like loop invariant code motion and redundant code elimination. In this paper we address the problem of performing this optimization interprocedurally. We use interprocedural partial redundancy elimination for placement of communication and communication preprocessing statements while compiling for distributed memory parallel machines.

This paper presents a unified framework for program optimization which subsumes (i) Loop invariant code motion, (ii) Common subexpression elimination, and (iii) Strength reduction. Use of this framework is shown to eliminate the control flow analysis costs and to widen the scope of conventional strength reduction.

In Static List Scheduling (SLS), initially the ALAP (As Late As Possible) algorithm is performed, followed by ASAP (As Soon As Possible) algorithm. The time interval for control steps and successor selection are the vital drawback of ASAP algorithm. Hence, in this paper, the optimized scheduling algorithm is proposed for High Level Synthesis (HLS), where the ALAP in SLS is followed by Force Directed Scheduling (FDS). The proposed scheduling algorithm is implemented in Icarus Verilog and targeted in ZC7020 FPGA board. The proposed optimized scheduling algorithm is evaluated in terms of control steps and resource utilization. The evaluation is carried out for various benchmarks such as, EW Filter, IIR filter, FIR filter, AR filter and Discrete Cosine Transform (DCT). The achieved results in terms of the control steps and resource utilization (i.e. LUT and Flip-flop) shows the proposed optimized scheduling algorithm outperforms the conventional Static List Scheduling (SLS) algorithm.

The subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC ZYNQ 7000 while obtaining metrics of hardware resource consumption, power efficiency, and execution performance. The tasks are as follows: determine the ways of implementing algorithms; choose the analysis criteria for multivariate experiment; implement algorithms using SIMD instructions on the ARM part of the given SoC; implement algorithms using High-Level Synthesis for the FPGA part; and measure and obtain the results for each signal topology. The used methods: High-Level Synthesis, optimization techniques based on vector instructions, and multivariate experiment analysis. The following results were obtained: for the given criteria and metrics. The FIR filter was implemented on the ZedBoard development platform with SoC ZYNQ 7000. The data were obtained from post-synthesis power analysis and dynamic SoC consumption using tools from Xilinx and Analog Devices. The corresponding IP blocks were implemented using High-Level Synthesis. The experiment was completed to obtain execution performance metrics. Conclusions. The scientific novelty of the obtained results is summarized as follows: the competitor analysis was performed for the set of implementations of the given algorithms deployed on the ZYNQ platform using both SIMD instructions and several HLS-based topologies for the FPGA-offload execution strategy. The analysis of the multivariate experiment was also completed for selected criteria, power consumption, filtering speed (inverse value – delay), and the amount of hardware costs as a percentage of the used resources.

We present an approach for implementing a formally certified loop-invariant code motion optimization by composing an unrolling pass and a formally certified yet efficient global subexpression elimination. This approach is lightweight: each pass comes with a simple and independent proof of correctness. Experiments show the approach significantly narrows the performance gap between the CompCert certified compiler and state-of-the-art optimizing compilers. Our static analysis employs an efficient yet verified hashed set structure, resulting in the fast compilation.

High-level synthesis (HLS) is a potential solution to increase the productivity of FPGA-based real-time image processing development. It allows designers to reap the benefits of hardware implementation directly from the algorithm behaviors specified using C-like languages with high abstraction level. In order to close the performance gap between the manual and HLS-based FPGA designs, various code optimization forms are made available in today’s HLS tools. This paper proposes a HLS source code and directive manipulation strategy for real-time image processing by taking into account the applying order of different optimization forms. Experiment results demonstrate that our approach can improve more effectively the test implementations comparing to the other optimization strategies.

Automatic systolic array generation has long been an interesting topic since manual designs usually require huge implementation efforts. Conventional automatic systolic array generation builds dependency graphs from algorithms, and iteratively maps computation nodes in the graph into processing elements (PEs) with time stamps that specify the sequences for nodes to operate within the PE. Sometimes this mapping will generate an array with I/O operations being distributed to all PEs, which causes complex design scheme and area overheads. The process to eliminate such I/O is called interior I/O elimination. This paper presents our approach for interior I/O elimination. We propose an automated compiler to map algorithms to systolic arrays. For any mapped array with interior I/O, the compiler analyzes the communication patterns and determines if interior I/O can be eliminated in the design. If so, the compiler eliminates the I/O and adds necessary modules in the design for data transfer. We demonstrate our approach on two important applications'matrix multiplication and convolutional neural network. With the help of interior I/O elimination, the designs generated by the compiler are able to achieve 591.4GFLOPs and 405.2GFLOPs, respectively.

Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a technique called loop shifting that incrementally exploits loop level parallelism across iterations by shifting and compacting operations across loop iterations. Our experimental results show that loop shifting is particularly effective for the synthesis of designs with complex control especially when resource utilization is already high and/or under tight resource constraints. In situations when further loop unrolling (or initiating another iteration of the loop body) leads to a sharp increase in the longest combinational path in the circuit and the circuit area, loop shifting is able to achieve up to 20% reduction in the input-to-output delay in the synthesized circuit. We implemented loop shifting within the SPARK parallelizing high-level synthesis framework and present results for experiments on designs derived from multimedia and image processing applications.

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.