RETRACTED: Batched matrix computations on hardware accelerators based on GPUs

In recent years, many cores architecture co-processors have become the main trend in high-performance computing area due to their powerful parallel computing capability. GPU is one of these promising high-performance computing co-processors and has been used in various applications for improvement. Sorting is a fundamental operation on computing area which can be used in a variety of applications. High efficient sorting algorithms can be achieved with the use of GPUs as well as challenges. On the one hand, GPU is a memory access sensitive hardware. On the other hand, many access on device memory are required in stages of sorting on GPU. In order to reduce the times of accessing device memory of sorting, we propose a Memory Access Reduced hybrid sort, an approach combining memory efficient radix sort and local sort. The local sort is implemented in two different ways. One is multiway bitonic sorting network (MAR-MBSN) in which the warp-shuffle instructions are taken advantage of. Another is radix and place sort (MAR-RPS). As the increasing require of high performance computing, multi-core GPUs have emerged. To fully use of the computing resources of GPU, two methods are applied for implementing our approach on dual-cores GPU. Experiments show that, compared to the CUB library sorting, MAR-MBSN has an up to 44% improvement and MAR-RPS gains an up to 3-fold speedup in local sort. As a result, MAR-MBSN and MAR-RPS achieves a speed up of no less than a factor of 1.5 and 1.66 respectively. Besides, multi-core GPU is introduced to implement our approaches and the factors relative to performance are analyzed.

Factorization and Inversion of a Million Matrices using GPUs: Challenges and Countermeasures

Today, accelerator cards like GPUs are an important constituent of HPC clusters. For certain GPU-intense applications, the trend is shifting toward multi-GPU systems with four or more GPUs per compute node. This can increase the performance per dollar and the performance per watt. The Linpack benchmark is the standard tool for measuring the compute performance of supercomputers. Its standard implementation, HPL, cannot make use of GPUs on its own and other GPU-enabled versions of HPL show reduced efficiency on multi-GPU systems with four or more GPUs per node. In previous efforts we have developed a GPU-accelerated Linpack implementation in particular for AMD GPUs, which we employed on several clusters of a couple of hundred nodes each. Gustafson's law predicts perfect weak scaling with the number of processor cores, but it is not directly applicable to the number of GPUs in a system due to shared resources. In this paper we develop a model for general relations between the number of GPUs and the minimum problem size required to use them efficiently taking into account the limited PCIe bandwidth, memory bandwidth, and CPU resources. Based on this, we present an approach to scale our Linpack implementation to eight GPUs and achieve good GPU utilization in Linpack on future systems. Finally, we examine how energy efficiency, which has improved significantly with dual-and quad-GPU servers, scales to many-GPU systems.

A constructive heuristic for the permutation flow shop scheduling problem with the objective of minimizing total completion time is proposed in this paper. It is constructed using a population-based technique and also the insertion rule similar to that presented in the Nawaz–Enscore–Ham (Omega 11:91–95, 1983) heuristic for the makespan criterion. We show, through computational results, that the proposed heuristic performs better than the heuristic of Woo and Yim (Comput Oper Res 25:175–182, 1998) for small and large problem sizes and the heuristic of Framinan and Leisten (Omega 31:311–317, 2003) for small and medium problem sizes. However, the relative performance of the heuristic of Framinan and Leisten improves compared to the proposed method when the job size increases. The time complexity of the proposed method has been shown to be less than those required by the existing heuristics. The average CPU time of the proposed heuristic is significantly less than the heuristic of Framinan and Leisten for large jobs.

Multipliers have a crucial role in many digital systems, especially in areas like signal processing, image filtering, etc. As the devices get smaller and faster, more innovative approaches are required to design these multipliers so that power usage is less and the design is also area-efficient. This is where VLSI(Very Large Scale Integration) techniques come into play. They basically help in the packing of millions of tiny components onto a single chip with great efficiency. By using the right VLSI techniques, multipliers that are both fast and energy-efficient can be built. This makes them an important part of today’s technology, starting from mobile devices to high-performance computing. In this project, a multiplier was designed that focuses on speed, area, and energy efficiency. The design was implemented using Verilog HDL and then synthesized using Xilinx Vivado Tools. In an ASIC flow Area, Power and Delay analysis were done using GPDK 45,90, and 180 nm. The conventional multipliers face significant challenges, including large area requirements, high power dissipation, and increased computational delay. These drawbacks increase as the bit-width increases, making them less suitable for energy-constrained applications. The AMUL multiplier architecture presented some noticeable improvements in speed and power efficiency when compared with conventional designs. It reduces the transistor count by employing a $4: 2$ compressor and input reordering, leading to improved speed and energy efficiency. For an 8-bit architecture, the design achieves delays of $68.4 \mathrm{~ns}, 203.6 \mathrm{~ns}$, and 598.7 ns for $45 \mathrm{~nm}, 90 \mathrm{~nm}$, and 180 nm nodes, respectively, with power consumptions of 2.75 uW, 5.20 uW, and 20.8 uW, representing substantial savings compared to exact multipliers. As the next step, the aim is to integrate this multiplier into larger digital processing systems to evaluate its real-world performance. Further optimization of the multiplier’s structure and exploring other design strategies may also help in refining its efficiency even more.

Heuristic methods for the optimal statistic median problem

Scheduling number of jobs in a single machine is a “Uni-machine job scheduling problem”. The mean of variation of job's waiting time is called Waiting time Variance (WTV). Minimization of WTV directly improves the quality of service (QoS) of systems involved with job scheduling. WTV minimization is a NP-hard problem. As a matter of fact minimization of the WTV on computer networks can lead to stable and predictable network performance. The main objective of this paper is to provide a secure and predictable computer and network systems by proposing a heuristic based novel approach to minimize the WTV. This approach illustrated with small size problems along with randomly new generated problems. The experimental results are compared with existing approaches. The experimental result shows the proposed approach gives best performance for the compared approaches and problems tested. The findings of intended algorithm are shown in the form of table for consonant problems.

Applications on today's massively parallel supercomputers rely on performance analysis tools to guide them toward scalable performance on thousands of processors. However, conventional tools for parallel performance analysis have serious problems due to the large data volume that may be required. In this paper, we discuss the scalability issue for MPI performance analysis on Blue Gene/L, the world's fastest supercomputing platform. We present an experimental study of existing MPI performance tools that were ported to BG/L from other platforms. These tools can be classified into two categories: profiling tools that collect timing summaries, and tracing tools that collect a sequence of time-stamped events. Profiling tools produce small data volumes and can scale well, but tracing tools tend to scale poorly. The experimental study discusses the advantages and disadvantages for the tools in the two categories and will be helpful in the future performance tools design.

The Adaptive Loop Filter (ALF) in the Versatile Video Coding (VVC) standard enhances visual quality but introduces a significant computational burden, posing a challenge for its implementation on resource-constrained devices. This paper presents a comprehensive evaluation of the ALF classification step, analyzing its execution time and energy consumption across multiple programming paradigms (scalar, SIMD, CUDA) on both a high-performance desktop and an embedded platform. Results show that on the high-performance desktop, SIMD optimization provides a substantial speedup over the scalar baseline with lower energy consumption, while the discrete GPU’s performance is limited by data transfer overhead. Conversely, the embedded system demonstrates a different landscape: its ARM CPU offers superior energy efficiency when compared to the desktop, and its integrated GPU’s runtime is dominated by kernel execution rather than data transfers. These findings underscore that the optimal ALF implementation is highly platform-dependent, hinging on the specific design trade-offs between processing speed and energy efficiency.

Solution method for the location planning problem of logistics park with variable capacity

Recently, FPGA-based CNN accelerators have demonstrated superior energy efficiency compared to high-performance devices like GPGPUs. However, due to the constrained on-chip resource and many other factors, single-board FPGA designs may have difficulties in achieving optimal energy efficiency. In this paper we present a deeply pipelined multi-FPGA architecture that expands the design space for optimal performance and energy efficiency. A dynamic programming algorithm is proposed to map the CNN computing layers efficiently to different FPGA boards. To demonstrate the potential of the architecture, we built a prototype system with seven FPGA boards connected with high-speed serial links. The experimental results on AlexNet and VGG-16 show that the prototype can achieve up to 21x and 2x energy efficiency compared to optimized multi-core CPU and GPU implementations, respectively.

Coverage is a typical problem in wireless sensor networks to fulfil the issued sensing tasks. In general, sensing coverage represents how well an area is monitored by sensors. The quality of a sensor network can be reflected by the levels of coverage and connectivity that it offers. The coverage problem has been studied extensively, especially when combined with connectivity and energy efficiency. Constructing a connected fully covered, and energy efficient sensor network is valuable for real world applications due to the limited resources of sensor nodes. In this paper, we survey recent contributions addressing energyefficient coverage problems in the context of static WASNs, networks in which sensor nodes do not move once they are deployed and present in some detail of the algorithms, assumptions, and results. A comprehensive comparison among these approaches is given from the perspective of design objectives, assumptions, algorithm attributes and related results.

Erlang is a concurrent language built to run on the BEAM virtual machine. This paper discusses the different approaches one can take to profile programs built on Erlang from both inside and outside BEAM and their inherent tradeoffs. It divides profiling and tracing tools into system and VM-level, com- pares both categories’ advantages and disadvantages in terms of performance and how trying to keep performance might minimize other aspects of the pro- filing, and describes how to take advantage of them both alone and together by combining their outputs to produce the best possible result.

The number of cores in a single chip in the nodes of high-end computing systems is on rise, due, in part, to a number of constraints, such as power consumption. With this, the size of the last level cache (LLC) has also increased significantly. Since LLCs built with SRAM consume high leakage power, power consumption of LLCs is becoming a significant fraction of processor power consumption. To address this issue, researchers have used embedded DRAM (eDRAM) LLCs which consume low leakage power. However, eDRAM caches consume a significant amount of energy in the form of refresh energy. In this paper, we propose ESTEEM, an energy saving technique for embedded DRAM caches. ESTEEM uses dynamic cache reconfiguration to turn off a portion of the cache to save both leakage and refresh energy. It logically divides the cache sets into multiple modules and turns off possibly different number of ways in each module. Microarchitectural simulations confirm that ESTEEM is effective in improving performance and energy efficiency and provides better results compared to a recently-proposed eDRAM cache energy saving technique, namely Refrint. For single and dual-core simulations, the average energy saving in memory subsystem (LLC+main memory) with ESTEEM is 25.8% and 32.6% respectively, and the average weighted speedup is 1.09x and 1.22x respectively. Additional experiments confirm that ESTEEM works well for a wide-range of system and algorithm parameters.

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible not regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised, because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This paper will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.