RETRACTED: Urban ecological forestry analysis based on FPGA and dynamic image sampling

Currently, the fast evolution of cameras in recent years has made them promising tools for diagnostics of Tokamak. The solution presented in this paper consists of a prototype of high-speed visible image acquisition and processing system (HVIAPs) dedicated for experimental advanced superconducting tokamak shape and position control. Graphics processing unit (GPU) and field-programmable gate array (FPGA) are typically used as accelerators or co-processors in addition to a CPU. Such a heterogeneous computing system can combine the advantages of its individual components. The main imaging equipment components used for this system are four high-resolution fast cameras equipped with fiber interface. Image data from the cameras are received by the frame grabber card based on the FPGA and transmitted to the GPU via the peripheral component interconnect express interface. The software support for the system includes low-level drivers and application programming interface libraries for all components and the algorithm developed for image processing. The offline image process results are compared to equilibrium fitting code, which is a commonly used reconstruction method, with an average error of 1.5 cm. The total processing time for one frame is less than 0.3 ms.

This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

WITHDRAWN: 3D Printing clothing design based on wireless sensors and FPGA

A three-dimensional (3D) laser scanning system is the main part of reverse engineering. It is a comprehensive technological system, including numerical control (NC), a laser, computer-aided design/manufacturing (CAD/CAM), precision mechanisms, computing image sampling, and image processing. Generally, it consists of a motion control system, an image sampling system, and an image processing system, etc. This paper focuses on introducing control principles, hardware constitutions, and software algorithms of the servo motion system, and analyzes and presents the hardware constitutions, software algorithms, and experimental results of the image sampling and processing system in great detail. Finally, the authors come to the conclusion that the errors all occur within the range ±0.1 mm.

The book focuses on the cost/area, performance and power consumption differences between Field-Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). These differences are referred to as the gap between FPGAs and ASICs and knowledge of this gap is fundamental for people who design FPGAs, who use FPGAs, or who are considering their use. This book reviews and examines the gap in two ways. The first portion of the book focuses on measurements of the silicon area, performance, and power consumption gap. This is done by comparing designs implemented on a commercial FPGA and using an ASIC methodology. Through this comparison, various trends are noted to elucidate some of the design choices that can narrow the gap. The latter half of the book focuses on the trade-offs that can be made in the creation of a FPGA to narrow the gap selectively. This is useful because silicon area, performance and power consumption are not equally important to all users of FPGAs. The book describes the approach used to investigate these trade-offs and it includes a detailed description of the transistor sizing tool developed to assist in this investigation. The scope of the trade-offs is then examined and the effect of these trade-offs on the FPGA to ASIC gap is considered. The idea of making cost and performance trade-offs has been considered in past works but this book explores the use of transistor-sizing to enable these trade-offs.

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and others. This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or converted into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. These efforts complicate and delay the conversion of FPGA designs to ASICs but must be considered by designers of microelectronic systems. Topics covered include: design flow; system partitioning; hardware description languages (HDLs); specifying behavioral control; specifying structural components; critical paths; placement and routing; technology choices; FPGA applications; rapid prototyping; retargeting; manufacturing defects; scan chain insertion; test vector generation; fault grading, and ASIC production

Morphology is an image algebra technique whereby the shape and structure of an input object is transformed by a smaller object called the structuring element. The two most fundamental morphological operations, erosion and dilation, are usually defined in terms of set operations. Alternatively they can be understood in terms of a convolution followed by a threshold. In this paper we describe an iterative acoustooptic (AO) morphological image processor. The input to the system is displayed on a 128 × 128 magnetooptic spatial light modulator, and the system utilizes an AO Bragg cell in the Fourier plane of a coherent optical correlator to generate the desired structuring element. Thresholding is performed electronically in an image processing system. The feedback necessary for multiple erosions and dilations is provided electronically via a single computer that controls both an image processing system in the output image plane and the MOSLM.

There is still no partial reconfiguration tool support on low-cost Field Programmable Gate Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA families by Xilinx. This forces the designers and engineers, who are using the partial reconfiguration capability of FPGAs, to use expensive families such as Virtex-4, Virtex-5 and Virtex-6 which are officially supported by partial reconfiguration (PR) software. Moreover, Xilinx still does not offer a portable, dedicated self-reconfiguration engine for all of the FPGAs. Self-reconfiguration is achieved with general-purpose processors such as MicroBlaze and PowerPC which are too overqualified for this purpose. In this study, we propose a new self-reconfiguration mechanism for Spartan-6 FPGAs. This mechanism can be used to implement large and complex designs on small FPGAs as chip area can be dramatically reduced by exploiting the dynamic partial reconfiguration feature for on-demand functionality loading and maximal utilization of the hardware. This approach is highly attractive for designing low-cost compute-intensive applications such as high performance image processing systems. For Spartan-6 FPGAs, we have developed hard-macros and exploited the self-reconfiguration engine, compressed Parallel Configuration Access Port (cPCAP) [1], that we designed for Spartan-3. The modified cPCAP core with block RAM controller, bitstream decompressor unit and Internal Configuration Access Port (ICAP) Finite State Machine (FSM) occupies only about 82 of 6,822 slices (1.2% of whole device) on a Spartan-XC6SLX45 FPGA and it achieves the maximum theoretical reconfiguration speed of 200MB/s (ICAP, 16-bit at 100MHz) proposed by Xilinx. We have also implemented a Reconfigurable Processing Element (RPE) whose arithmetic unit can be reconfigured on-the-fly. Multiple RPEs can be utilized to design a General Purpose Image Processing System (GPIPS) that can implement a number of different algorithms during runtime. As an illustrative example, we programmed the GPIPS on Spartan-6 for switching between two applications on-demand such as two-dimensional filtering and block-matching.

The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Guneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

Hardware acceleration using field programmable gate arrays (FPGAs) has become increasingly popular for computationally intensive digital signal processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable computer aided design (CAD) flow and performance, they have poor power characteristics when compared to direct application specific integrated circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large non-recurring engineering (NRE) costs. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. Several coarse-grained fabric architectures proposed during the last decade have been focused on performance and area-efficient architectural techniques. Even though power is becoming one of the critical design concerns for semiconductor industry, this issue has not been adequately addressed in the existing coarse-grained fabric architectures. In this paper, a low-power and high-performance hardware acceleration engine for DSP style applications is described. This reconfigurable fabric model is generic and parameterizable allowing design parameters to be adjusted within the architecture. The impact of varying different design parameters such as functional unit granularity, and multiplexer cardinality are studied for their implications on power and performance. The low-power fabric was designed to operate within the SuperCISC processor architecture designed at the University of Pittsburgh

New VLSI high throughput parallel structures for arbitrary rate non integer ratio sample rate conversion are presented in the paper. High throughput Sample Rate Converters (SRC) find application in high data rate Software Defined Radio (SDR) where a large degree of flexibility is required to support varied sample rates. Parallel Signal Processing implementations offer higher throughput for lower clock speeds. This makes them ideal for high data rate modem implementations on FPGA's or in power limited ASIC designs. The Farrow structure offers unique advantages ideal for parallel implementation. These unique qualities allow the utilization of novel reduced complexity parallel finite-length impulse response (FIR) filters. The structures presented in this paper are suitable for implementation on application specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). Results shown here are for implementation on FPGAs with varying orders of parallelization.

This thesis aims to develop an embedded image processing board, which can be used to realize various image feature extraction and processing algorithms for robotic applications. The circuitry of this image board can be divided into two parts, one is for a digital signal processor (DSP) and the other for a field programmable gate array (FPGA). A low power, small size CMOS image sensor with YUV4:2:2 image format and 512x480 pixel size is adopted for image acquisition. The DSP module is mainly used for implementing image processing algorithms, while the FPGA module for lower level image processing and sensor control functions. In this work, the TMS320C6414TGLZ7 DSP from Texas Instruments Corporation and the EP2C35F672C6 FPGA from Altera Corporation were selected for the image board. In this work, speeded-up robust features (SURF) algorithm has been successfully realized on the developed image board. An USB interface with average throughput of 22MB/sec works to transfer acquired image frames and extracted SURF descriptors to a personal computer, where feature matching is executed. Experimental results show that the refresh period of frame grabbing is about 33.5ms. When the number of SURF descriptor is equal to 64, the computing time is about 417.5ms; when the number of SURF descriptor is equal to 199, the computing time is about 985ms. The typical matching rate varies from 70.2% to 20%, depending on the threshold of the patterns used in feature extraction.

The increasing complexity of instrumentation in science and industry has lead to a growth in the use of Application Specific Integrated Circuits (ASICs). Solutions using ASICs are very cost efficient in high volume production. They are also very valuable when instrument volume, functionality, and reliability are the main issues. In the standard cell approach, the ASIC designer is allowed to use predefined functional building blocks as an aid in the design process. This is advantageous when using a high-level design methodology for the digital circuits. Preverified models exist for the analogue and the digital standard cells, and thus the standard cell approach is very similar to using Field Programmable Gate Arrays (FPGAs). However, using standard cells, as opposed to full custom design techniques, leads to degraded flexibility and performance in terms of circuit density and speed. On the other hand one gains design time.

Software-based radios implemented on general-purpose processors are cheaper, easier, and faster to develop, maintain, and upgrade than hardware-based equivalents. Unfortunately, today's general-purpose processors are not fast enough to process certain waveforms. The current alternative is to use application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) for all the signal processing. These operate at very high speeds but are dramatically more expensive and require lengthy development cycles. A single, often small, block is responsible for the bulk of signal processing in a large class of radios. It is therefore very wasteful to implement all the signal processing in a high-speed device such as an ASIC or FPGA. In this paper, we present a software-centric architecture that offloads only the most computationally expensive tasks to an FPGA. The resultant system combines the advantages of both platforms, while minimizing the disadvantages of each. An open-source software radio platform is combined with a consumer off-the-shelf (COTS) FPGA development board to create a hardware-accelerated multichannel receiver. The FPGA is efficiently utilized by partitioning the device into multiple accelerator regions and taking advantage of runtime partial reconfiguration to reconfigure each region as needed during operation. Comparisons between a software-only receiver and a hardware-accelerated implementation are performed.

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely.