Reversible SSG Gate for Implementing Parity Checker Generator and Magnitude Comparator

Quantum-Dot Cellular Automata (QCA) is a unique technology that substitutes the CMOS technology. QCA is an innovative nanotechnology for binary logic synthesis. A Transistor less Nano computing device that has high speed, very less power usage and dissipation, more packing density. Parity generator and checker circuits mainly used in error recognition and correction circuits. However, the previous designs deficient in practical reliability because they negotiate with most common design metrics. In this paper, a unique Parity Generator and Checker circuit constructed having less area, less number of clock zones and low latency. To construct parity generator and checker circuit a unique Ex-or gate is proposed. The proposed 4-bit Parity Generator and Checker circuit is having 15 & 16 cells respectively, which decreases the area to 0.0168µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compared to best existing designs until date. To check the working and performance of the proposed design, QCA Designer version 2.0.3 is used which is familiar tool for QCA designs.

Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.

All-optical parallel parity generator circuit with the help of semiconductor optical amplifier (SOA)-assisted Sagnac switches

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.

Heat is an important issue in VLSI circuits. But the reversible logic gives zero amount of heat dissipation. So, its an important role in nanotechnology, less energy complementary metal oxide semiconductor [CMOS] designs etc. It has been realized that quantum computing is one of the latest technologies using reversible logic gates. It is contemplating that accumulation extension of transistor density, energy desolation will command their limits in ordinary technologies. In ordinary area or range during the logic influence bits of orientation is erased resulting gratification of power in powerful amount. In the terms of reversible logic results are not lost.[1] This minimize the delays but at the amount of little hardware. So we can use reversible logic technology for decreasing the energy dispersion, heatwave dissipation, increasing rapidness etc. So it is used to maximize the speed and reducing energy consumption. In this, we can describe following reversible logic gates like fredkin, peres, Feynmen and toffoli gate etc.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates. Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates which are stepping stones in design and synthesis of any complex reversible logic based synthesis.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates .Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates and propose a novel reversible DS gate which will be stepping stone in design and synthesis of any complex reversible logic based synthesis.

The reversible logic synthesis is a multi-objective optimization problem with rigorous constraints such as prohibiting the feedback and fan-out, and the same number of inputs and outputs, so it is difficult to be solved by general synthesis methods. Moreover, the synthesis methods of reversible logic circuits are very different from that of existing irreversible logic circuits. To make improvements in the capability and effectiveness of reversible logic synthesis, this paper proposes an algorithm of reversible logic gate-level evolutionary synthesis using multi-objective adaptive discrete differential evolution based on Pareto optimal. The synthesis experiments are conducted for a set of benchmark reversible logic circuits which are widely used in the reversible logic synthesis tests. The experiment results show that the proposed synthesis algorithm can give attention to multiple synthesis objectives at the same time, and has the capability to automatically synthesize the better reversible logic circuits, which verifies the feasibility and effectiveness of the proposed synthesis algorithm.

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA &amp; SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.

The Parity Generators and checkers are crucial block in Central Processing Unit especially in the process of Error Detection and correction during data transmission. In this work, the three-bit Quantum Cellular Automata (QCA) even parity generator have been proposed using Layered T AND and OR Gate. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. Moreover, the other QCA design metrics such as Effective Area, O-Cost, Cost <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">α</sub> , Irreversible Power Dissipation, and Complexity are analyzed for the proposed Parity Generator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner.

Reversible logic gate has gained importance in recent times due to its low power dissipation and less information loss. QCA on the other hand has low power consumption and has applications in reversible logic. In this paper, a 4×2 priority encoder is proposed which is based on reversible logic implemented in QCA. Firstly, this paper discusses about QCA layout design of Fredkin gate and Universal Reversible Logic Gate (URLG). Secondly, this paper uses reversible logic gate (both Fredkin and URLG) to design a 4×2 priority encoder in QCA.

Any sequential learning task relies on the idea of connecting previous time-stamp information to the immediate present time-stamp task to predict the future. The underlying challenge is to understand the hidden patterns in the sequence by means of analyzing short- and long-term dependencies and temporal differences. Recurrent Neural Networks (RNNs) and their variants, such as Long Short-Term Memory (LSTM) are widely used in problem domains like speech recognition, Natural Language Processing (NLP), fault prediction, and language translation modeling over the past few years. Higher accuracy demands complex LSTM network models which lead to high computational cost, area overhead, and excessive power consumption. Reversible logic circuit synthesis, in the context of ideally Zero heat dissipation, has emerged as a new research paradigm for low power circuit designs. In this paper, we have proposed a novel design of LSTM architecture using reversible logic gates. To the best of our knowledge, the proposed approach is the first attempt to implement a complete feedforward LSTM circuit using only reversible logic gates. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 17% reduction in overall power dissipation compared to traditional networks. The proposed approach also has better scalability than the classical design approach.

The Reversible logic gates implement the functions which are having one to one mapping between the input and output. Unlike irreversible logic circuits the information cannot be lost as the input vector can be recovered from the corresponding output vector. The dissipation of heat is also less in reversible logic gates. Therefore the reversible logic gates have immense number of applications in Low power CMOS design, quantum computing, Nano technology and digital signal processing. This paper proposes a novel 4×4 bit reversible fault tolerant MAC unit. The MAC unit Composed of a multiplier, adder and an accumulation unit. The Ripple Carry Adder and multiplier used in the proposed work were designed using parity preserving gates. The basic building blocks for adder and multiplier used were IG gate, Fredkin gate which are parity preserving gates. Therefore the proposed MAC unit has characteristic attribute of detecting any errors in output side. The synthesis and simulation was done by using Xilinx software and Model Sim Simulator.

Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.