Layered T Parity Generators using Quantum-dot Cellular Automata

Quantum-Dot Cellular Automata (QCA) is a unique technology that substitutes the CMOS technology. QCA is an innovative nanotechnology for binary logic synthesis. A Transistor less Nano computing device that has high speed, very less power usage and dissipation, more packing density. Parity generator and checker circuits mainly used in error recognition and correction circuits. However, the previous designs deficient in practical reliability because they negotiate with most common design metrics. In this paper, a unique Parity Generator and Checker circuit constructed having less area, less number of clock zones and low latency. To construct parity generator and checker circuit a unique Ex-or gate is proposed. The proposed 4-bit Parity Generator and Checker circuit is having 15 & 16 cells respectively, which decreases the area to 0.0168µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compared to best existing designs until date. To check the working and performance of the proposed design, QCA Designer version 2.0.3 is used which is familiar tool for QCA designs.

Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.

Missing-cell defects in QCA wires: The ground and excited electronic states perspectives

The objective is to design a new reversible logic gate for implementing parity checker and generator logic circuit and a magnitude comparator logic circuit with minimum computational time. Power dissipation seems to be a major drawback in all conventional irreversible logic circuits. As a solution to this, circuits can be constructed using reversible logic gates. According to the principle of reversible logic a new 3X3 gate named as SSG gate has been proposed. SSG gate has the ability to realize the following logic functions like XOR, NOR, OR, NOT, XNOR, AND and COPY. The proposed work can be implemented on a floating point subtractor and multiplier design. The proposed SSG gate is used to test the functionality of a even parity checker and generator circuit and it is compared with the circuit realized using existing Feynman gate. The comparative result shows that SSG parity checker and generator consumes 0.67 seconds less time compared with the existing gate. The comparative result of the 2-bit magnitude comparator designed using proposed SSG gate and with the existing reversible gate1 and Gate2 shows that the computation time for SSG gate comparator is reduced by 0.33 seconds with the existing reversible gate1 and gate2. Keywords: Magnitude Comparator, Parity Checker, Parity Generator, Reversible Logic

All-optical parallel parity generator circuit with the help of semiconductor optical amplifier (SOA)-assisted Sagnac switches

Quantum Cellular Automata (QCA) is a transistor-less computation model that addresses the problem of device interconnection and density which holds the promise of high speed and fewer sizes compare to the Complementary Metal Oxide Semiconductor (CMOS) design. In this study, the design of 4-bit down asynchronous counter which is the fundamental block of the digital technology using new D-Flip Flops (D-FF) layouts is discussed. This D-FF is designed using majority gates. The FF clock inputs are not driven by the same clock and each FF output depends on the previous output. This design finds its application in nanotechnology fields including medical field to monitor the patient’s activity by utilizing timer based tools. The design of 4-bit down asynchronous counter is simulated in the QCA design tool.

The use of optical signal in logic and data processing is not new. Lots of optical systems are already implemented using light as the data signal. In this context polarization based encoding of data is an important method. Again to avoid any unwanted error in data signal sometimes it becomes essential to check the data signal, especially during transmission of data through large distance. Checking the parity of the data signal during transmission and reception is one way to ensure errorless transmission of data. In this communication the authors propose a method to implement an all-optical parity generator and checker using polarization encoded light signal. The scheme uses the switching capacity of isotropic nonlinear material, where the 1st order nonlinearity is absent but the 2nd order nonlinearity is present. This scheme can be used to check whether any error has occurred during transmission of optical data signal. As parity checking is an essential component in any communication system and it ensures the correctness of sending data at the receiving point, so the proposed all- optical system can exhibit a strong application in optical communication as well as in computation.

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.

Quantum-dot cellular automata (QCA) are a new paradigm in nanoscale technology with high frequency and low power consumption capabilities. This work presents a low complexity two-input XOR gate, which achieves low power consumption compared to prior ones using an efficient five-input majority gate. To show the novelty of this structure, different bits even parity generators are addressed. The result shows proposed parity generators are more superior over the existing designs. We show a 32-bit even parity generator, which requires 40% less cell count and saves 50% area occupation over the previous best design. QCA Designer-2.0.3 and QCA Pro have been considered to evaluate the accuracy of presented designs and to evaluate the power dissipation respectively.

A method has been developed for evaluating central processing unit (CPU) coverage by automatically injecting faults into actual CPU hardware while it is executing relevant test software. A special hardware test fixture is used which contains the CPU under evaluation, program and data memory, and a terminal interface. The test fixture is connected to a microcomputer controller and an in-circuit read only memory (ROM) emulator. The faults injected are stuck-at-1, stuck-at-0, and open on the appropriate integrated circuit pins, plus the altered state of every microprogram memory bit. The effect of each fault is determined by observing the status of the monitor. Data reduction is performed after each run on a separate host computer, and summary results are tabulated. N digital avionics systems the central processing unit (CPU) is obviously the dominant functional element, upon which many other elements are dependent in order to perform correctly related interface and control tasks. Normally, there are arrays of system monitors, in both hardware and software, which have an inherently overlapping capability to detect CPU malfunctions. The combined effectiveness of these monitors determines the total CPU fault coverage. However, since many of these monitors are themselves dependent upon CPU operation, there is a critical topdown relationship between the monitors which must be considered. In particular, a software monitor is of little subsequent value in the presence of a CPU fault unless one of the two following conditions is present. 1) It is actually executed, and it produces the planned fault detection results, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. 2) It causes fault detection elsewhere when it is not executed, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. In simplest terms, software monitors depend upon a rational CPU; that is, a CPU which is at least able to follow the normal program flow without making addressing or branching errors. If this is not the case, then how can one guarantee that the software monitor is executed? If it is possible to detect the fault of concern without executing the software monitor, then why is the monitor present? The point is that it is critically necessary to have a CPU monitoring scheme which establishes the minimum CPU fault coverage that is required to support all other monitoring activity. Such a monitoring scheme must straddle the hardware-software boundary so that external communication is absolutely guaranteed. In the simple terms introduced in the preceding, such a monitor must be able to detect all faults resulting in irrational CPU operation. In most modern digital avionic systems, the monitor which does these things is the so-called watchdog monitor (WDM) (or alternately the heartbeat or deadman timer monitor). The WDM usually operates in relation to the timer

In this paper, a universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out register (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter and receiver is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit. The baud rate of the transmitter and receiver is 4 Mbps using the system clock of 64 MHz’s. Implementation, simulation, and synthesis is done Xilinx Vivado 2016.2 version tool. The design is verified using simulated waveform and synthesized on the FPGA Zed board.

Combinational logic devices are readily available as standard ICs for performing complex digital functions and they are hazard free. The operation of multiplexers, demultiplexers, decoders, encoders, parity generators, parity checkers and comparators are presented. The application of the devices is also presented.

Communication between any two electronic devices requires set of rules. These set of rules are called protocols. They ensure that data communication is done without any corruption. UART- Universal Asynchronous Receiver Transmitter is a serial communication protocol. UART consists of two main modules; UART Transmitter and UART Receiver. The transmitter section of UART consists several blocks like an FSM, a pulse Generator, odd/even Parity Generator, and Shift Register. In the similar way UART receiver consists an Edge Detector, FSM, shift register, even/odd parity checker and a B aud Rate Generator. Since the baud rate generator of both transmitter and receiver is same, so the baud rate(baud clock) of transmitter and receiver is also same. The UART transmitter has a 11-bit data frame. First bit is 1 start bit (indicates start of transmission), followed by 8-bit data that carries the information, 1 parity bit that indicates the parity(I this project odd parity is considered) and 1 stop bit (end of transmission). The baud rate generated in the work is 4 Mbps with input system clock of 64MHz frequency. The design and verification of UART is done using the Verilog HDL(Hardware Description Language). Xilinx Vivado-2020.2 version tool is us to implement the simulation and synthesis of UART. The targ FPGA board used for synthesizing the UART is ZedBoard, may be used for IoT applications.

We have implemented the Martini force field within Lawrence Livermore National Laboratory's molecular dynamics program, ddcMD. The program is extended to a heterogeneous programming model so that it can exploit graphics processing unit (GPU) accelerators. In addition to the Martini force field being ported to the GPU, the entire integration step, including thermostat, barostat, and constraint solver, is ported as well, which speeds up the simulations to 278-fold using one GPU vs one central processing unit (CPU) core. A benchmark study is performed with several test cases, comparing ddcMD and GROMACS Martini simulations. The average performance of ddcMD for a protein-lipid simulation system of 136k particles achieves 1.04 µs/day on one NVIDIA V100 GPU and aggregates 6.19 µs/day on one Summit node with six GPUs. The GPU implementation in ddcMD offloads all computations to the GPU and only requires one CPU core per simulation to manage the inputs and outputs, freeing up remaining CPU resources on the compute node for alternative tasks often required in complex simulation campaigns. The ddcMD code has been made open source and is available on GitHub at https://github.com/LLNL/ddcMD.

A new algorithm for massively parallel calculations of electron correlation energy of large molecules based on the resolution of identity second-order Møller-Plesset perturbation (RI-MP2) technique is developed and implemented into the quantum chemistry software NTChem. In this algorithm, a Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) hybrid parallel programming model is applied to attain efficient parallel performance on massively parallel supercomputers. An in-core storage scheme of intermediate data of three-center electron repulsion integrals utilizing the distributed memory is developed to eliminate input/output (I/O) overhead. The parallel performance of the algorithm is tested on massively parallel supercomputers such as the K computer (using up to 45 992 central processing unit (CPU) cores) and a commodity Intel Xeon cluster (using up to 8192 CPU cores). The parallel RI-MP2/cc-pVTZ calculation of two-layer nanographene sheets (C150H30)2 (number of atomic orbitals is 9640) is performed using 8991 node and 71 288 CPU cores of the K computer.