Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)

Communication between any two electronic devices requires set of rules. These set of rules are called protocols. They ensure that data communication is done without any corruption. UART- Universal Asynchronous Receiver Transmitter is a serial communication protocol. UART consists of two main modules; UART Transmitter and UART Receiver. The transmitter section of UART consists several blocks like an FSM, a pulse Generator, odd/even Parity Generator, and Shift Register. In the similar way UART receiver consists an Edge Detector, FSM, shift register, even/odd parity checker and a B aud Rate Generator. Since the baud rate generator of both transmitter and receiver is same, so the baud rate(baud clock) of transmitter and receiver is also same. The UART transmitter has a 11-bit data frame. First bit is 1 start bit (indicates start of transmission), followed by 8-bit data that carries the information, 1 parity bit that indicates the parity(I this project odd parity is considered) and 1 stop bit (end of transmission). The baud rate generated in the work is 4 Mbps with input system clock of 64MHz frequency. The design and verification of UART is done using the Verilog HDL(Hardware Description Language). Xilinx Vivado-2020.2 version tool is us to implement the simulation and synthesis of UART. The targ FPGA board used for synthesizing the UART is ZedBoard, may be used for IoT applications.

The UART(Universal Asynchronous Receiver and transmitter) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. SPI is a common technology used nowadays for communication with peripheral devices where we want to transfer data speedily and with in real time constraints. In the existing work data acquisition system for underground has been designed for counters triggered by surface detectors and they have used UART and SPI protocol for the communication with dedicated processor. In this paper we have used Xilinx 12.4i and SPARTAN 3E FPGA to implement the whole system. The hyper terminal is used to check the UART protocol and 12 bit DAC MCP4922 used for check SPI protocol. The proposed work can provides both protocol effectively for the wireless serial communication. These serial protocols mainly used in Zigbee wireless technology.

The communications link in a space program is a crucial point for upgrading its performance by handling data between spacecraft bus and payloads, because spacecraft`s missions are related to the data handling mechanism using communications ports such as a controlled area network bus (CAN Bus) and a universal asynchronous receiver and transmitter (UART). The NEXTSat-1 has a lot of communications ports for performing science and technology missions. However, the top level system requirements for the NEXTSat-1 are mass and volume limitations. Normally, the communications for units shall be conducted by using point to point link which require more mass and volume to interconnect. Thus, our approach for the novel communications link in the NEXTSat-1 program is to use CAN and serializer and deserializer low voltage differential signal (SerDesLVDS) to meet the system requirements of mass and volume. The CAN Bus and SerDesLVDS were confirmed by using already defined communications link for our missions in the NEXTSat-1 program and the analysis results were reported in this study in view of data flow and size analysis.

Many Internet of Things (IoT) applications are emerging and evolving rapidly thanks to widespread open-source hardware platforms. Most of the high-end open-source IoT platforms include built-in peripherals, such as the universal asynchronous receiver and transmitter (UART), pulse width modulation (PWM), general purpose input output (GPIO) ports and timers, and have enough computation power to run embedded operating systems such as Linux. However, each IoT platform has its own way of configuring peripherals, and it is difficult for programmers or users to configure the same peripheral on a different platform. Although diverse open-source IoT platforms are widespread, the difficulty in programming those platforms hinders the growth of IoT applications. Therefore, we propose an easy and convenient way to program and configure the operation of each peripheral using a user-friendly Web-based software framework. Through the implementation of the software framework and the real mobile robot application development along with it, we show the feasibility of the proposed software framework, named SoEasy.

This chapter describes the design and scientific results from a new tri-axial magnetometer for atmospheric and space studies. The new instrumentation features multi-frequency (1 KHz -1.5 MHz), multi-bandwidth (1 Hz -10 KHz), multi magnetic field measurement range, low-power and re-configurable operation. This novel architecture is based on producing a programmable receiver independent of the fluxgate sensor used. Any ring-core, race-track or parallel type fluxgate sensor may be connected to the input and a working system is produced within hours. The current implementation is based on a novel shielded 3-dimensional sensor optimised for previously unseen low-power consumption compared to existing tri-axial macro-sensors. As a fully digital system the sensor's output is sampled after the amplification stage. The full extent of the complex solar wind -magnetospheric -ionospheric system is measured by the magnetometer, due to the receiver's programmable dynamic range (DR) and the programmable cross-correlator integration time. The field-programmable gate array (FPGA) hardware implementation yields to a programmable filtering scheme that selects different centre frequencies and desired signal bandwidths. The output is directly in nT to avoid any unnecessary software post-processing calibration procedures and to ensure compatibility of results amongst users. The user selects either the magnetic field's vector components or the total intensity to be present at either the universal asynchronous receiver and transmitter (UART) or the fast 10/100 Mbps Ethernet communications ports. The development of the magnetometer's sensor is based on the implementation of a novel design methodology for producing optimised fluxgate sensors for low-power consumption. The sensor is qualified for both ground-based and spaceborne observations. The results are of interest to the aerospace and defence industries, since fluxgate sensors exist in airborne and spaceborne systems for decades. Lowering power consumption is followed by simplification of the accompanying electronic circuits. The system is constantly being enriched by research results from an ongoing collaboration with NASA's Jet Propulsion Laboratory (JPL) on a different project for future missions (Dekoulis & Murphy, 2008). The presented system is complementing existing and under development state-of-the-art systems, such as, scalar/vector magnetometers. The system acts as a pathfinder for future high-resolution planetary exploration missions.

Design of a micro-UART for SoC application

In the March 1987 issue of Hispania, Christopher Davison reported the results of the first efforts to establish an electronic bulletin board for the American Association of Teachers of Spanish and Portuguese. Building upon these efforts, an electronic bulletin board now exists on the University of Toledo's VAX 11/785 mini-computer and is available for anyone to use twenty-four hours a day, seven days a week. You are cordially invited to do so. The following information will help you get started. In addition to your computer, you will need a modem (a device that translates the computer's electronic signals into sounds that can be transmitted over the telephone lines), and a communications program (software capable of generating and interpreting those sounds). Some of the more popular programs are ASCII Express, Softerm, Apple Access II (Apple IIe), CrossTalk, Hayes Smartcom, PC Talk, ProComm (IBM family), MacTerminal, Red Ryder Hayes Smartcom II, and Microphone (Macintosh). For additional information, you may wish to consult Howard Cohen's article Telecommunications and the Foreign Language Teacher in the May, 1986 issue of Hispania. The A.A.T.S.P. Electronic Bulletin Board is designed to allow several people access at the same time, so there should be no problems with busy signals when you dial in. You can use virtually any microcomputer, modem and communications program, provided you follow the appropriate protocols, e.g., the baud rate, the number of data and stop bits, the parity, and the duplex. Although these terms might seem complicated to the computer novice, their technical definitions are unnecessary: they are simply settings which determine the manner and speed with which information flows through the phone lines from one computer to another. In order to connect to the bulletin board, you should set your communications program as follows: * 300, 1200 or 2400 baud; * 7 data bits; * 1 stop bit; * space parity; * full duplex.

Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.

Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.

Embedded memory systems are integral to modern VLSI designs, constituting a significant portion of chip area and directly impacting system reliability and performance. As semiconductor memories become denser and operate at higher frequencies, they are increasingly prone to various faults such as stuck-at, transition, coupling faults etc. Undetected memory failures can lead to critical system malfunctions, making efficient memory testing a fundamental requirement in hardware verification and validation. To ensure robustness, various memory testing algorithms have been developed, often serving as the foundation for Memory Built-in Self-Test (MBIST) methodologies. In this paper, we analyse the FSM (finite state machine) based FPGA implementation of two widely used memory test algorithms, March C- and Checkerboard, and assessing their efficiency in terms of area, power consumption, and delay. These algorithms are implemented in Verilog, synthesized on Xilinx Vivado – 2016.2, and deployed on the Nexys 4 DDR Artix-7 FPGA. Our results provide a comparative evaluation of these algorithms, demonstrating their effectiveness in detecting memory faults and highlighting their suitability for FPGA-based memory testing and verification.

All-optical parallel parity generator circuit with the help of semiconductor optical amplifier (SOA)-assisted Sagnac switches

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.

The objective is to design a new reversible logic gate for implementing parity checker and generator logic circuit and a magnitude comparator logic circuit with minimum computational time. Power dissipation seems to be a major drawback in all conventional irreversible logic circuits. As a solution to this, circuits can be constructed using reversible logic gates. According to the principle of reversible logic a new 3X3 gate named as SSG gate has been proposed. SSG gate has the ability to realize the following logic functions like XOR, NOR, OR, NOT, XNOR, AND and COPY. The proposed work can be implemented on a floating point subtractor and multiplier design. The proposed SSG gate is used to test the functionality of a even parity checker and generator circuit and it is compared with the circuit realized using existing Feynman gate. The comparative result shows that SSG parity checker and generator consumes 0.67 seconds less time compared with the existing gate. The comparative result of the 2-bit magnitude comparator designed using proposed SSG gate and with the existing reversible gate1 and Gate2 shows that the computation time for SSG gate comparator is reduced by 0.33 seconds with the existing reversible gate1 and gate2. Keywords: Magnitude Comparator, Parity Checker, Parity Generator, Reversible Logic

The problem of at the edge training of deep neural network (DNN) is being pursued by researchers extensively with several approaches that establish novelty at different levels, like algorithm, communication between networks, techniques involving data - bit width representation, etc. The work in this paper addresses one of the possibilities of training DNNs at the edge of the network by architecting the hardware needed to perform training at the edge with the objective of improving upon resource utilization and lowering power consumption. These objectives are key metrics by which application deployment on edge devices are evaluated. Further, this paper proposes a novel hardware architecture for both inference and training of DNNs with a Central and Pre-Fetch finite state machine (FSM) being designed to ensure efficient transfer of weights and biases from memory needed for computations pertaining to inference and training. The detailed hardware units designed for both inference and training have been illustrated with the resource utilization, power and timing reports for their implementation carried out on Xilinx ZCU104 embedded board using the Xilinx Vivado 2019.2 synthesis tool. The results prove, both the novelty and ability of the hardware architecture to be used for edge-based deployment of DNNs with learning.

This paper introduces a method to implement UART based on Field Programmable Gate Array(FPGA). Its baud rate can be set and the states can be read. The structure of this system is divided in modularization so that can fit the method Top-Down. The hard core of this system is implemented with finite state machine (FSM)[1]. It makes the logic of control more intuitionistic and more briefness. The efficiency of the design is improved in a wide range. Simulating experiments, present at last to proved the validity and reliability in the whole design.