Design and simulation analysis of UART IP Core

We propose 400-Gb/s (16 × 25 Gb/s) optical transmitter and receiver modules for on-board interconnects using polymer waveguide (PWG) arrays. Four four-channel vertical cavity surface emitting laser and PIN photodiode arrays are used in the optical transmitter and receiver modules. A 16-channel PWG array with a length of 140 mm and a pitch of 62.5 μm is used as a short-reach optical signal transmission medium in the module. The 25-Gb/s optical eye diagrams of the all output channels utilize PWG transmissions and exhibit good performance in the transmitter module, with a signal-to-noise ratio (SNR) of over 8.01, peak-to-peak time jitter below 11.70 ps, and mask margin of over 31.5%. In the best-performance channel of the receiver module, the peak-to-peak time jitter and SNR of the eye diagram are 10.34 ps and 10.76, respectively, and the receiver sensitivity is approximately −2.6-dBm under a bit error rate of 10−12. The optical transmitter and receiver modules utilizing PWG transmissions were designed and fabricated to realize 400-Gb/s on-board interconnects.

In this paper, a universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out register (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter and receiver is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit. The baud rate of the transmitter and receiver is 4 Mbps using the system clock of 64 MHz’s. Implementation, simulation, and synthesis is done Xilinx Vivado 2016.2 version tool. The design is verified using simulated waveform and synthesized on the FPGA Zed board.

Communication between any two electronic devices requires set of rules. These set of rules are called protocols. They ensure that data communication is done without any corruption. UART- Universal Asynchronous Receiver Transmitter is a serial communication protocol. UART consists of two main modules; UART Transmitter and UART Receiver. The transmitter section of UART consists several blocks like an FSM, a pulse Generator, odd/even Parity Generator, and Shift Register. In the similar way UART receiver consists an Edge Detector, FSM, shift register, even/odd parity checker and a B aud Rate Generator. Since the baud rate generator of both transmitter and receiver is same, so the baud rate(baud clock) of transmitter and receiver is also same. The UART transmitter has a 11-bit data frame. First bit is 1 start bit (indicates start of transmission), followed by 8-bit data that carries the information, 1 parity bit that indicates the parity(I this project odd parity is considered) and 1 stop bit (end of transmission). The baud rate generated in the work is 4 Mbps with input system clock of 64MHz frequency. The design and verification of UART is done using the Verilog HDL(Hardware Description Language). Xilinx Vivado-2020.2 version tool is us to implement the simulation and synthesis of UART. The targ FPGA board used for synthesizing the UART is ZedBoard, may be used for IoT applications.

Authors propose a hardware based approach for reliable encryption in wireless network using Cellular Automata (CA). Distinct layers of encryption have been utilized in proposed model for enhancing data security. Transmitter and receiver modules are designed for performing state transition based encrypted activities. Transmitter module is required for capturing environmental turbulences (noise) from a specific geographical location and send encrypted signal to receiver module through wireless network. Receiver module analyses received signal after decryption for desired activities based on real time situations. Different hardware components are selected and compared based on market study targeting efficient construction of proposed modules. Time complexity and code break complexity are measured using different key lengths, keysets, and data sizes for proposed CA based encryption scheme achieving unique results in hardware based cryptography system. Encryption key length, index, and keyset are required for computing code break complexity in design model. Large data size is effectively managed to calculate protection ratio and reliability factor for realizing efficient protectiveness and accuracy. Comparative study between existing encryption technique and proposed CA based encryption technique is established based on time complexity and code break complexity.

This paper describes the electrical and physical characteristics of 20 new solid-state devices developed for TD-3. Among them are new high-frequency planar, epitaxial, NPN silicon transistors which are used in intermediate-frequency amplifiers and in the FM deviator. The microwave power for the transmitter and receiver is supplied from a three-stage varactor multiplier chain which uses three new epitaxial silicon varactor diodes. A high-quality epitaxial silicon varactor diode pair is the up-converter in the transmitter modulator. A new epitaxial gallium arsenide Schottky barrier mixer diode assures a low noise figure for the receiver modulator. Two point-contact silicon IF and RF monitor diodes were developed using the same miniature package in which the transmitter modulator and receiver modulator diodes are encapsulated. Two very stable diffused silicon diodes provide a stable output from the FM deviator; in-process preaging at accelerated conditions is used to assure satisfactory stability. Two new epitaxial silicon Schottky barrier diodes are used in the IF amplifier-limiter and discriminator circuits, which require a nonlinear resistance with negligible capacitance and recovery time. Stringent voltage breakdown, corona and mounting requirements for the high voltage power supply rectifiers were satisfied by molding two high-voltage diode rectifier assemblies in a high-dielectric plastic. The need for a pure variable resistance in the IF variolosser was satisfied by the development of a new silicon PIN diode.

This paper presents a control and acquisition platform design method of travelling wave dielectrophoresis microchip based on SOPC technique. The direct digital frequency synthesis (DDS) modeling is built by using the digital signal processing (DSP) development tool of FPGA, DSP Builder. By the controlling of NIOSII, which embedded in the FPGA (CyclonII EP2C35) of Altera corp., the four-phase DDS module outputs four channels AC signals with the same magnitude, and their phase of four channels AC signals are 0deg, 90deg, 180deg and 270deg, respectively. They supply control signals for the travelling wave ITO electrodes array. The travelling wave dielectrophoresis electric field is created by the four-channel AC signals, it drives biological particles direction moving to achieve different biological particles separating in the microchannel of dielectrophoresis micochip. Adopting the custom I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C module achieves the configuration of 3-Megapixel CMOS image sensor, MT9T001, which achieves the contactless detection of different biological particles. The design of DDS IP core based on DSP Builder, the design of custom I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C module, the hardware framework and software design of control system is mainly introduced in article. The correctness and practicability of design method is testified by simulation results.

We experimentally demonstrate the implementation of 10 Gbps high-speed mid-infrared (MIR) free-space optical (FSO) communication, by means of our developed robust high-speed MIR transmitter and receiver modules. Such modules can enable frequency down- and up-conversion between 1550 nm and 3594 nm based on difference frequency generation (DFG) in MgO-doped periodically poled LiNbO3 (MgO: PPLN). The MIR transmitter generates 5.34 dBm power at 3594 nm for input powers of 33 dBm at 1550 nm and 37 dBm at 1083 nm. The MIR receiver regenerates -24.5 dBm power at 1550 nm for input powers of -1.2 dBm at 3594 nm and 36.7 dBm at 1083 nm. The eye diagram of regenerated 1550 nm signal is clear, and both for the on-off keying (OOK) and differential phase shift keying (DPSK) modulation, the power penalties compared with back to back (BTB) signals are lower than 3.5 dB measured at bit error ratio (BER) of 1E-6. According to our analyses, the system supports variable data rate, wavelength, and modulation format. Furthermore, the optical and electrical components are well integrated and fixed in MIR transmitter and receiver modules, which exhibit long-term stability and can be applied to field experiments.

This paper describes optical transmitter and receiver modules for package-to-package interconnection in broadband switching networks such as an asynchronous transfer mode switch fabric. These modules, which include the multiplexer and demultiplexer, can reduce the number of connections and the problem of skew between links. Five-channel optical transmitter and receiver modules were fabricated and demonstrated at 2.8 Gbit/s with a power dissipation of 4.5 W per channel. Moreover, temperature-insensitive optical interconnection was successfully demonstrated by driving a laser with a constant bias current over the threshold and by deducting the optical signal offset. The output power of the transmitter module was -4.2 dBm. Nonuniformity of the transmitter output powers across the range of optical channels was <2.1 dB. Receiver sensitivity for a bit error rate of 10/sup -11/ was -9.3 dBm. Nonuniformity of the receiver sensitivities was <1.5 dB. The power penalty of the receiver sensitivity due to crosstalk was 1 dB. The connection distance was >250 m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Design of IP Cores in Finite Field for Error Correction

This paper reports on the development and experimental characterization of a high data-rate communication link at 240GHz with highly-integrated direct-conversion quadrature transmitter and receiver modules implemented in 130nm SiGe HBT technology with ft/fmax of 350/550 GHz. Both modules employ a low-cost chip-on-board packaging scheme with single-chip TX and RX front-end circuits accommodating wideband silicon lens-integrated wire ring on-chip antennas. The key highlights of the developed hardware are its high RF and IF operation bandwidths available from the printed-circuit board-level. With the preliminary wireless transmission tests, a 20Gbps and a 24Gbsp transmission speed with an EVM of 24% was demonstrated for BPSK and QPSK modulation schemes at a distance of 90cm with no channel equalization applied. For a 10Gbps BPSK, an error-free communication link could be established.

We developed transmitter and receiver modules with Ti:PPLN waveguide operated as difference frequency generator to convert a signal (lambda <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ~ 1550 nm) to the mid infrared (lambda <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> ~ 3800 nm) and back again.

In this paper, a graphene-based electromagnetic imaging system working in 140–220 GHz frequency band for nonintrusive analysis of 3D artwork is presented. A single-stage high-order frequency multiplier is used to generate the signal at the transmitter module, whereas the single-stage high-order subharmonic mixer acts as a signal detector at the receiver. Both modules exploit the nonlinear response of graphene sheets excited by an incident electromagnetic wave, to generate harmonic components and mixing products of the input signals, respectively. The transmitter and the receiver modules were implemented through an additive manufacturing process. The resulting electromagnetic imaging system prototype was applied to the analysis of ceramic vessels, showing its ability to detect enclosed objects and to obtain information in cross-sectional planes. Furthermore, the geometrical parameters and filling material characterization can be obtained by processing the frequency response of the scattered field.

This paper proposes a novel medium access control scheme for low cost, single-hop wireless networks where the source nodes have a transmitter module but no receiver module and hence they can only transmit data to a sink but cannot receive any control signals, like an ACK or NAK, from any other node. The goal of the proposed scheme is to provide QoS (in terms of packet delivery probability) to the nodes in such a network, where the existing schemes like polling or scheduled transmissions, CSMA and ARQ will be ineffective because of the unavailability of a receiver module at the nodes. The proposed scheme uses distributed control and allows the nodes to transmit each packet an optimal number of times at random instants in time within the packet generation interval. We define two optimization problems based on minimizing total network traffic and maximizing the delivery probability of the class of nodes requiring the highest QoS, respectively, and develop mathematical formulae and efficient algorithms to solve them. Numerical analysis and simulation results show that our scheme can provide high QoS to networks of different sizes.

In this paper, a passive control scheme based on the fractional-order calculus is proposed. We study the modified complex projective synchronisation between two identical fractional-order complex chaotic systems, and its application in the secure communication. The fractional-order complex chaotic Lorenz system is employed to encrypt the emitted signal. In the transmitter module, the information signal is modulated into one parameter of the Lorenz system. It is assumed that the same parameter is unknown in the receiver module. In order to synchronise two systems with different initial conditions, the controllers and an appropriate parameter update rule are designed. Theoretical analysis and numerical simulations show that this method is feasible and robust to some extent in the presence of channel noise.

Ultrasound represents a very compact, low cost method that is non-invasive and does not involve ionizing radiation. A new A-mode ultrasound pulser-receiver system, which digital control module is based on FPGA chip, has been designed and implemented. The pulser-receiver system consists of three parts: digital signal processing module, high frequency pulser and receiver module. The pulser was programmed to generate unipolar pulse trains with 1 cycle, at frequency of 10 MHz, repetition frequency of about 1 KHz, and amplitude of 80 V to drive a 10MHz piezoelectric transducer. Clear ultrasonic pulse echo has been measured in the receiver. Simulations of key components and measured signal of pulser-receiver system have been shown. These results indicate that the system implementation has reached a good performance.