Scalable High Voltage CMOS technology for Smart Power and sensor applications

In the search for new physics, the Large Hadron Collider at CERN will be upgraded around year 2025, increasing its integrated luminosity by an order of magnitude. For the Inner Tracker (ITk) of the ATLAS experiment, the elevated levels of radiation, pile-up and data rate will require a complete replacement. Active pixel sensors built in sub-micron High Voltage CMOS (HV-CMOS) processes are candidates for the ITk outer pixel detector layers. Being high voltage tolerant, thus supporting drift-based charge collection, they allow to build radiation hard detectors in industry standard technology. On-sensor signal processing permits replacing complex and cost-intensive hybridisation techniques by simpler ones, ultimately leading to fully monolithic devices. In this thesis, sensors built in the ams H18 180nm process were investigated as hybrid detectors. Several design versions were characterised in laboratory and in-beam measurements. The FE-I4 Telescope, a particle tracker for beam based detector characterisation was built to facilitate measurements on HV-CMOS sensors. Its construction and performance as well as the findings on detection performance of the HV-CMOS prototypes, especially after irradiation, are presented.

This paper presents an integrated multichannel neurostimulator ASIC with improved power management efficiency. The stimulator features transcutaneous closed-loop power control that enables optimum power transfer in spite of the coupling variation as well as the variation in the stimulation threshold/current. A programmable adaptive supply in the high voltage (HV) domain is further proposed to minimize the power dissipation during the active stimulation mode in terms of stimulus current/electrode impedance inconsistencies. The stimulator prototype, including the power management, the digital control as well as a 16 channel stimulation frontend, is fabricated in AMS 0.35μm HV CMOS technology. In measurements, automatic supply voltage adaptation from 13.1V to 8V with running stimulations has been achieved, resulting in maximum power saving of 40% for the implantable circuit.

A time-gated 4×128 Single Photon Avalanche Diode (SPAD) line array with a 512-channel Time-to-digital converter (TDC) has been designed and fabricated in a 0.35 μm high voltage CMOS technology for pulsed Raman spectroscopy. In Raman spectroscopy the SPAD array can be designed as a line array with a high fill factor because electronics can be designed on either side of the SPAD array. In this paper cross talk measurements of the array have been carried out to investigate the probability of the cross talk between adjacent SPADs in an array with high density. Measurements showed a cross talk probability of 0.11% with a pitch of adjacent SPADs of 32 μm. In addition, the largest probability of the cross talk was measured to occur with a short delay.

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration for the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. The HV-CMOS technology is a commercial integrated circuit process with the advantages of monolithic readout and fast charge collection. A front-end test platform of CaRIBOu (Control and Readout Itk BOard) and a testbeam Telescope based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, have been developed for the HV-CMOS sensor study and characterization in testbeam experiments. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between detector front-end electronics and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for both the CaRIBOu and the testbeam Telescope. It has been deployed successfully in the testbeam at the CERN SPS H8 beamline in August 2017. The test results show that the readout system is capable of sensor calibration and readout of a high-density pixel detector with high trigger rate in testbeam experiments.

This paper presents an application specific integrated circuit (ASIC) for use in a three-dimensional microchannel neural interface. The device is assembled with seven stacked ASICs with silicone microchannels instrumented in between. Each ASIC comprises tripolar electrodes for seven channels allowing recording or stimulation from any one of the 49 microchannels. The ASIC is implemented in 0.35μm high-voltage CMOS technology and occupies an active area of 4 mm2. The device has been tested demonstrating recording of 1 mV signals, and current controlled stimulation in the range of 5 μA to 500 μA (with 40 V compliance) and up to 50 kHz stimulation frequency. The device overcomes limits on numbers of connected microchannels in previous designs.

A monolithic quasi-fixed-frequency DC-DC boost converter with a modified-adaptive-off-time (MAOF) control is presented. To achieve a quasi-fixed-frequency in whole loading range, the new MAOF control is able to overcome the frequency variation problems naturally exist in traditional adaptive-off-time control in both continuous- and discontinuous-conduction-mode (CCM and DCM) operations. The MAOF control boost converter was implemented with a 0.35µm High Voltage (HV) CMOS process. With 3V – 4.2V input voltage, 10V – 14V output voltage and 30mA – 300mA load current range, simulated results show that the switching frequency keeps constant at 960kHz to within ±5% across the whole operation range.

The present paper describes the development of high voltage CMOS process line-up (5/11/20/30V) for display driver applications, based on 0.13mum CMOS process with aluminum metallization. The advantages are smaller size of SRAM bit cell and lower process cost. High voltage CMOS devices, 1.5V(LV) logic CMOS, 5.5V(MV)CMOS, poly-Si resistor (HR/MR), MOS-capacitor, SRAM and OTP are available. 10.8mum device pitch of 30V CMOS and good electric characteristics were successfully achieved. Thanks to the low cost and wide voltage options, various kind of display driver ICs can now be realized in smaller die size and lower cost

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

A NUMBER of MOS developments have been attempted to provide operation at voltages higher than 200V1-?. Among these, DSA6 MOST seem to have a promising future. This paper will describe a high voltage, DSA MOS IC which operates in excess of 400V. It was designed as a driver for electroluminescent displays . Low voltage logic and thirty-two high-voltage output transistors are integrated on a single chip. The device consists of a pair of layers patterned as concentric conductive annular strips above which a layer of metal with a circular gap is deposited. This configuration and final passivation over the metal layer permit encapsulation in a plastic package. The high voltage DSA MOST was proposed earlier with a 71 substrate, a Diffusion-Self-Aligned structure, lightly doped drift region(N-), and a field plate extended from the draine lectrode? The drift region of this device was not covered by field plates; i.e., an offset gate structure. If the field plate is extended to cover all of?the drift region in these devices, the electric field at the edge of the drift region will be enhanced and the breakdown voltage reduced.

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in 0.18- ㎛ high voltage CMOS, the proposed LDO shows up to 200 ㎃ load current with 0.2V dropout voltage for 1㎌ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 ㎷, 7.5㎂, and higher than 1 ㎒, respectively.

A sensor chip for a capacitively coupled pixel detector (CCPD53) has been designed and produced in a 180 nm high voltage CMOS (HVCMOS) technology on a high resistivity wafer with deep p-well option. Capacitively coupled pixel detectors are a simple and low-cost alternative to classical hybrid detectors. They rely on capacitive signal transmission between the sensor chip and the readout chip. A pixel detector with small pixel size can be made without small pitch bumps. The CCPD53 sensor chip contains a pixel matrix of 64 × 40 pixels, each 25 μm × 50 μm in size. The digital output signals of a group of 16 pixels are encoded and the 8-bit output is connected to signal transmission pads arranged with pitch of 50 μm. The pad geometry has been chosen in a way to fit the geometry of the pixel readout ASIC developed by RD53 collaboration at CERN. The PHOTON readout chip has been implemented in the UMC 180 nm CMOS technology. It allows counting and integration of charge signals. The chip consists of a matrix of 32 × 30 identical square pixels with 150 μm × 150 μm size. In this paper the sensor and the readout chip will be described and the measurement results presented.

This paper presents a fully integrated high voltage charge pump which enables a reconfigurable, energy-efficient multi-band transceiver. Using a high voltage CMOS technology from Austriamicrosystems and a 4-phase charge-pump (DC/DC converter) circuit architecture, up to 120 V supply voltage can be generated from a 3.7 V DC battery using this monolithically integrated circuit. The very small footprint of this solution enables the integration of this multi-band transceiver in mobile devices, whereas the concept of reconfigurability can also be applied to fixed transceiver installations to optimize power efficiency.

In this paper, we present a novel, piezoelectric actuator driver topology that combines high-voltage actuator driving in the range of −50 V-to +100 V with piezoelectric reliability. The output waveform is generated by a novel capacitor clamping circuit (patent# PCT/EP2016/066134) with programmable rise-and fall times implemented in a 0.35 um high-voltage bulk CMOS technology optimized for capacitive light-load (2 nF- to 8 nF) operation. The novel piezoelectric actuator driver consists of a negative voltage generator and a degradation regulator integrated onto a single chip. The smart driver electronics is optimized towards reliable piezoelectric operation by taking fatigue and electrical overstress into account. The novel piezoelectric actuator driver is the first step towards self-regulated electrical compensation of piezoelectric actuator degradation which promises increased actuator lifetime and reliable operation.

A monolithic optical receiver containing four single-photon avalanche diodes (SPADs) fabricated in 0.35-μm high-voltage (HV) CMOS is introduced and compared with two 4-SPAD receivers realized in pin-photodiode CMOS belonging to the same process family. This HV-CMOS SPAD receiver achieves sensitivities of −55.1 dBm at 50 Mbit / s and −52.0 dBm at 100 Mbit / s, both with digital processing, a bit error rate (BER) of 2 × 10 − 3, and return-to-zero coding using a wavelength of 642 nm. Also at 143 Mbit / s, this BER is achievable. This receiver is especially interesting for applications in which low light intensities can be expected, such as quantum key distribution, optical communications from deep space, and visible light communication for short-range consumer applications.