Development of FELIX based readout system for HV-CMOS sensor testbeam

In the search for new physics, the Large Hadron Collider at CERN will be upgraded around year 2025, increasing its integrated luminosity by an order of magnitude. For the Inner Tracker (ITk) of the ATLAS experiment, the elevated levels of radiation, pile-up and data rate will require a complete replacement. Active pixel sensors built in sub-micron High Voltage CMOS (HV-CMOS) processes are candidates for the ITk outer pixel detector layers. Being high voltage tolerant, thus supporting drift-based charge collection, they allow to build radiation hard detectors in industry standard technology. On-sensor signal processing permits replacing complex and cost-intensive hybridisation techniques by simpler ones, ultimately leading to fully monolithic devices. In this thesis, sensors built in the ams H18 180nm process were investigated as hybrid detectors. Several design versions were characterised in laboratory and in-beam measurements. The FE-I4 Telescope, a particle tracker for beam based detector characterisation was built to facilitate measurements on HV-CMOS sensors. Its construction and performance as well as the findings on detection performance of the HV-CMOS prototypes, especially after irradiation, are presented.

High-voltage CMOS is a promising technology for the pixel sensor of tracking detectors in the collider experiments. Extensive studies are being carried out by the ATLAS Collaboration to investigate the possibility of using the HV-CMOS technology in the HL-LHC upgrade of the ATLAS inner tracker detector. The CaRIBOu (Control and Readout Itk BOards) is a modular test system developed to test the HV-CMOS pixel sensor prototypes and demonstrators. This test system consists of pixel sensor specific front-end chip boards, a control and readout board (CaR board), a central interface board and the back-end DAQ system. Currently, two DAQ solutions are available for the CaRIBOu system, one is based on the FELIX (front-end link eXchange) readout system and the other is based on the Gigabit Ethernet link. Various testbeam experiments have been carried out with the CaRIBOu system since 2015 for the pixel sensors fabricated by the AMS HV-CMOS 180 nm and 350 nm technologies. The test results show that this test system is very flexible and could be adapted to the test of different pixel sensors with minimum effort, and the performance meets the testbeam requirements.

After the breakthrough discovery of the Higgs Boson, more collision data produced by the LHC is needed, to study the properties of the Higgs Boson in more detail and to search for rare new physics phenomena. The High-Luminosity LHC (HL-LHC) upgrade will increase the luminosity to 7.5 · 103434 cm-2 s-1 with up to 200 simultaneous p-p interactions per bunch crossing, exposing the detectors to significant challenges concerning bandwidth and radiation tolerance. ATLAS is building a completely new all-silicon Inner Tracker (ITk) to deal with these matters.The smallest functional building blocks of the ITk in the central outer layers of the Pixel detector, the Outer Barrel (OB) region, are the so-called Loaded Local Supports (LLS). These LLS are multi-module strcutures and feature-complete detector units, operated with CO_2 cooling and connected to a full Interlock and Detector Control (DCS) system. The readout chain covers full optical to electrical conversion, using the lpGBT and the VTRX+ as well as the Front End Link EXchange (FELIX) readout system.Before the final production is rolled out, the first pre-production LLS had to undergo a thorough set of tests to ensure the functional and thermal integrity of the detector and to validate the loading procedure, which can potentially alter module performance due to module handling and services interconnections.This paper aims to give an overview of the OB LLS, describe the particular LLS which underwent testing, the test setup, as well as the tests which were performed. Finally, the test results will be presented.The results show very good performance of the LLS, with almost no degradation due to the thermal stress and the mechanical stresses caused by the loading procedures and operation.

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

The High-Luminosity Large Hadron Collider (HL-LHC), scheduled to start operating in 2030, aims to increase the instantaneous luminosity by a factor of 10 compared to the LHC. To match this increase, the ATLAS experiment has been implementing a major upgrade program divided into two phases. The first phase (Phase-I), completed in 2022, introduced new trigger and detector systems that have been used during the Run 3 data taking period which began in July 2022. These systems have been used in conjunction with the new Data Acquisition (DAQ) Readout system, based on a software application called Software Readout Driver (SW ROD). SW ROD receives and aggregates data from the front-end electronics via the Front-End Link eXchange (FELIX) system and passes aggregated data fragments to the High-Level Trigger (HLT) system. During Run 3, SW ROD operates in parallel with the legacy Readout System (ROS) at an input rate of 100 kHz. For the Phase-II, the legacy ROS will be completely replaced with a new system based on the next generation of FELIX and an evolution of the SW ROD application called Data Handler. Data Handler has the same functional requirements as SW ROD but must be able to operate at an input rate of 1 MHz. To facilitate this evolution the SW ROD has been implemented using plugin architecture. This contribution presents the design and implementation of the SW ROD application for Run 3, along with the strategy for its evolution to the Phase-II Readout system. It discusses the lessons learned during Run 3 and describes the challenges that have been addressed to accomplish the demanding performance requirements of HL-LHC.

The ATLAS Insertable B-Layer (IBL) is the innermost layer of pixel detectors, and was installed in May 2014 at a radius of 3.3 cm from the beam axis, between the existing Pixel detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and occupancy, is the first large scale application of 3D sensors and CMOS 130 nm technology. The IBL detector construction was completed within about two years (2012 – 2014), and the key features and challenges met during the IBL project are presented, as well as its commissioning and operational experience at the LHC.

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

The LHCb Silicon Tracker Project

The ATLAS experiment at the Large Hadron Collider is currently preparing major detector upgrades to meet the requirements of the High Luminosity LHC (HL-LHC), scheduled to begin in 2026. With the radiation damage and high density of tracks expected at the HL-LHC, the current Inner Detector would be inoperable, and will instead be replaced by an all-silicon Inner Tracker (ITk). The ITk consists of two sub-systems: a pixel detector close to the beam pipe, and a strip detector at larger radii. This paper presents results from an extensive design and prototyping effort for the ITk strip detector, including studies of the sensors, electronics, and support structures. The performance of the detector has been validated through testbeams, simulations, and thermal and electrical prototypes. Plans for the forthcoming production phase are also presented.

The successful pre-production delivery of strip sensors for the new Inner Tracker (ITk) for the upgraded ATLAS detector at the High Luminosity LHC (HL-LHC) at CERN was completed and based on their performance full production has commenced. The overall delivery period is anticipated to last 4 years to complete the approximately 22000 sensors required for the ITk. For Quality Assurance (QA), a number of test structures designed by the collaboration, along with a large area diode and miniature version of the main sensor, are produced in every wafer by the foundry Hamamatsu Photonics K.K (HPK). As well as Quality Control (QC) checks on every main sensor, samples of the QA pieces from each delivery batch are tested both before and after irradiation with results after exposure to neutrons, gammas or protons to fluences and doses corresponding to those anticipated after operation at the HL-LHC to roughly 1.5 times the ultimate integrated luminosity of 4000 fb-1. In this paper the procedures are presented and the studies carried out to establish that the seven ITk QA Strip Sensor irradiation and test sites meet all the requirements to support this very extensive programme throughout the strip sensor production phase for the ITk project.

The ATLAS experiment is preparing for the High-Luminosity LHC (HL-LHC) upgrade, which will require the substitution of the current Inner Detector (ID) with a new all-silicon Inner Tracker (ITk). This work presents the results of the ITk Pixel system test, focusing on module performance, power consumption, data transmission and cooling efficiency, during detector integration. The results validate the system's readiness for the extreme conditions expected at the HL-LHC.

Italian-cluster technical solutions for the Quality-Control tests to the pixel-modules of the ATLAS Inner Tracker for High Luminosity LHC

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 µm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 µm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 µm HVCMOS technology to 0.18 µm and beyond as well as to currents of up to 8 A.

To maintain sensitivity to new physics in the coming years of Large Hadron Collider (LHC) operations, A Toroidal LHC ApparatuS (ATLAS) collaboration has been working on upgrading a portion of the front-end (FE) electronics and replacing some parts of the detector with new devices that can operate under the much harsher background conditions of future LHC runs. The legacy FE of the ATLAS detector sent data to the data acquisition (DAQ) system via the so-called Read Out Drivers (RODs) custom-made VMEbus boards devoted to data processing, configuration, and control. The data were then received by the Read Out System (ROS), which was responsible for buffering them during the High-Level Trigger (HLT) processing. From Run 3 onward, all new trigger and detector systems will be read out using new components, replacing the combination of the ROD and the ROS. This new path will feature an application called the Software Read Out Driver (SW ROD), which will run on a commodity server receiving FE data via the Front-End Link eXchange (FELIX) system. The SW ROD will perform event fragment building and buffering as well as serving the data on request to the HLT. The SW ROD application has been designed as a highly customizable high-performance framework providing support for detector-specific event building and data processing algorithms. The implementation that will be used for Run 3 of the LHC is capable of building event fragments at a rate of 100 kHz from an input stream consisting of up to 120 MHz of individual data packets. This document will cover the design and the implementation of the SW ROD application and will present the results of performance measurements executed on the server models selected to host SW ROD applications during Run 3.

In preparation for the High Luminosity LHC (HL-LHC) runs, the ATLAS inner detector will be completely replaced with an all silicon Inner Tracker (ITk). Hybrid silicon pixel modules will be used for the innermost tracking layers, and silicon micro-strip detectors will be used the outer layers of the tracker. During the production of the detector, the sensors, readout electronics, and other components will undergo a series of quality control (QC) and quality assurance tests. Defects in the fabrication of the sensors will be flagged early in the manufacturer's and ATLAS QC tests. A study of the influence of sensor defects was performed to assess the characteristics of these defects in completed modules, and whether any defect posed a risk to the operation of the front-end readout electronics. All defects were found to have no impact on the performance of the front-end readout electronics for healthy amplifier channels, and defects that short the coupling between the strip implant and the metal readout electrode were only noticeable for strip leakage currents in excess of 250 nA, beyond the end-of-life currents expected for most sensors at the HL-LHC.