Upgrade of the BOC for the ATLAS Pixel Insertable B-Layer

Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

To maintain sensitivity to new physics in the coming years of Large Hadron Collider (LHC) operations, A Toroidal LHC ApparatuS (ATLAS) collaboration has been working on upgrading a portion of the front-end (FE) electronics and replacing some parts of the detector with new devices that can operate under the much harsher background conditions of future LHC runs. The legacy FE of the ATLAS detector sent data to the data acquisition (DAQ) system via the so-called Read Out Drivers (RODs) custom-made VMEbus boards devoted to data processing, configuration, and control. The data were then received by the Read Out System (ROS), which was responsible for buffering them during the High-Level Trigger (HLT) processing. From Run 3 onward, all new trigger and detector systems will be read out using new components, replacing the combination of the ROD and the ROS. This new path will feature an application called the Software Read Out Driver (SW ROD), which will run on a commodity server receiving FE data via the Front-End Link eXchange (FELIX) system. The SW ROD will perform event fragment building and buffering as well as serving the data on request to the HLT. The SW ROD application has been designed as a highly customizable high-performance framework providing support for detector-specific event building and data processing algorithms. The implementation that will be used for Run 3 of the LHC is capable of building event fragments at a rate of 100 kHz from an input stream consisting of up to 120 MHz of individual data packets. This document will cover the design and the implementation of the SW ROD application and will present the results of performance measurements executed on the server models selected to host SW ROD applications during Run 3.

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The main TileCal upgrade will occur when preparing for the high luminosity operation. This (Phase 2) upgrade is scheduled around 2022. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. An ambitious upgrade development program is pursued to study different electronics options. Three options are presently being investigated for the front-end electronic upgrade. The first option is an improved version of the present system built using discrete components, the second alternative is based on the development of a dedicated ASIC, and the third is the development of a new version of the “QIE” based on the one developed for Fermilab. For the off-detector electronics a new back-end architecture is being developed, the so-called “super” Read-Out Driver (sROD). A demonstrator prototype read-out for a slice of the calorimeter with most of the new electronics, but also compatible with the present system, is planned to be inserted in ATLAS already in mid 2014 (at the end of the phase 0 upgrade).

A multi-channel PCI express readout board for fast readout of large pixel detectors

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system.This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

In this paper we present the performance of two algorithms currently running in the Tile Calorimeter Read-Out Driver boards for the commissioning of ATLAS. The first algorithm presented is the so called Optimal Filtering. It reconstructs the deposited energy in the Tile Calorimeter and the arrival time of the data. The second algorithm is the MTag which tags low transverse momentum muons that may escape the ATLAS muon spectrometer first level trigger.Comparisons between online (inside the Read-Out Drivers) and offline implementations are done with an agreement around 99% for the reconstruction of the amplitude using the Optimal Filtering algorithm and a coincidende of 93% between the offline and online tagged muons for the MTag algorithm. The processing time is measured for both algorithms running together with a resulting time of 59.2 μs which, although above the 10 μs of the first level trigger, it fulfills the requirements of the commissioning trigger ( ∼ 1 Hz). We expect further optimizations of the algorithms which will reduce their processing time below 10 μs.

The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the low-voltage current of the FE-I4 chip was measured. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionising Dose (TID) and temperature has been tested with X-ray irradiations. This paper presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

During the first LHC long shutdown (2013/14) a new innermost pixel layer will be added to the present ATLAS Pixel Detector. The Insertable B-Layer (IBL) is a high-reliability, ultra light and radiation hard Pixel Detector assembled with 3D n-in-p and planar n-in-n pixel sensors. Facing the effects of increased luminosity and radiation damage, IBL is expected to improve the b-tagging efficiency, help with pattern recognition performance and add tracking precision with respect to the current detector. Single and double chip modules are loaded on local mechanical support, in the form of 14 staves arranged in cylindrical barrel around the beam pipe. The production of the modules has already started, aiming for a total production of 24 staves including spares. Systematic Quality Assurance (QA) and Quality Control (QC) plans concerning modules, staves and flex from production to final assembly have been put in place. QA is performed in several collaborating institutes and final validation before installation in the ATLAS experiment will be carried out at CERN. Dedicated set-ups have been constructed in order to perform the full chain of QAlQC tests on the production staves. A CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cooling system is used to cool the pixel modules down to -35°C and an electronic chain similar to the final one has been developed. Furthermore a linear motion system carrying two 241 Am sources with an activity of 41 MBq each is mounted over the stave in order to perform a final characterization of the sensor's performance. The realization of source scans on the 24 production staves permits to analyze the response of sensors to radiation, to easily identify dead pixels, and to provide data for an eventual re-calibration of the charge calibration. The setup and first results obtained on prototype staves are described in detail.

TileCal is the central hadronic calorimeter of the ATLAS experiment at the LHC collider at CERN. The Read-Out Drivers (ROD) are the core of the off-detector electronics. The main components of the RODs are the Digital Signal Processor (DSP) placed on the Processing Unit (PU) dautherboards. This paper describes the DSP code and its performance with calibration and real data. The code is divided into two different parts: the first part contains the core functionalities and the second one the reconstruction algorithms. The core acts as an operating system and it controls the configuration, the data reception, transmission, online monitoring and the synchronization between front-end data and the Trigger information. The reconstruction algorithms implemented on the DSP are the Optimal Filtering (OF), Muon Tagging (MTag) and Missing ET (MET) calculation. The OF algorithm reconstructs the for each TileCal cell the amplitude and time of the deposited energy. This reconstructed energy is used by the MTag algorithm to tag low transverse momentum muons that may escape the ATLAS muon spectrometer Level 1 trigger whereas the MET algorithm computes the total transverse energy and the projection on X and Y for the entire module that will be used by the Level 2 trigger system. The DSP code performance has been validated with offline reconstruction comparison. The DSP performance has been evaluated using calibration data from Charge Injection System.

This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much lower speed. The CDR is able to track maximum frequency deviation of ±286.78 ppm between the incoming data and the local reference clock at 12.5Gb/s. The CDR occupies a chip area of 18700um2 and consumes 30.30mW of power at 12.5Gb/s.

Internet based applications are mostly based on a reliable transport service. TCP (transmission control protocol) is one of the protocols responsible for applications performance. Mobile users access to Internet services through 2.5 and 3 Generation networks, which have a significant latency due to error mechanisms introduced at the link layer, as well as transmission delays in the radio access networks. High latency produces interaction with timers of upper protocols. Data rate is other limiting characteristic on these networks. Moreover, data rate changes during a TCP connection due to mobility. TCP can adapt its rate when slow data rate changes thanks to its self-clocking propriety. In case of a sudden change, TCP performance is degraded due to spurious retransmission, and the activation of its congestion control mechanisms. This paper will show the effects and optimization of some TCP parameters over GPRS (general packet radio service) and 802.11b real networks.

Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction.

In order to solve the high bit error rate (BER) caused by rate oscillation in traditional Data Rate Change (DRC) algorithm, an improved DRC algorithm based on Adaptive Frame Length (AFL) was proposed. Firstly, the frame length and transmission rate of the initial transmission were determined by the parameters of the current channel and the information of previous empirical values. Then, if two frames with the same length were successively sent in the transmission process, the frame length would be accordingly increased. If the retransmission failed twice in a row, the frame length would be halved in the next transmission. Finally, the frame error rate was calculated based on the current frame length. The data rate would be updated If the value was less than the present threshold. Compared with RapidM DRC, the average bit error rate of the link decreased by 4.8 percentage points, and the link availability increased by 10 percentage points. The experimental results show that the proposed algorithm can eliminate the rate oscillation and improve the communication capability of the HF communication system.

The HF radio band is very important for military operations, enabling communications beyond line-of-sight. To deal with the variability of the Ionosphere, several technologies have emerged in the last years, like automatic Link Quality Analysis (LQA), Automatic Link Establishment (ALE) and Data Rate Change (DRC) algorithms. In this paper, two DRC algorithms are assessed — namely, Trinder and RapidM — and improved versions of these algorithms are proposed: Avoiding Cut-Off State (ACOS) and Bit Error Optimization (BEO). The first proposal reduces the occurrences of link cut-offs (corresponding to bit error rates higher than 10−3); the second proposal, besides increasing the link availability, eliminates data rate oscillations. When compared to the original versions of the algorithms, both proposals showed significant improvements in all of the considered link assessment metrics, either when evaluated in a simulation environment, or in real field propagation tests.