FE-I4 pixel readout chip and IBL module

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system.This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

A multi-channel PCI express readout board for fast readout of large pixel detectors

During the first LHC long shutdown (2013/14) a new innermost pixel layer will be added to the present ATLAS Pixel Detector. The Insertable B-Layer (IBL) is a high-reliability, ultra light and radiation hard Pixel Detector assembled with 3D n-in-p and planar n-in-n pixel sensors. Facing the effects of increased luminosity and radiation damage, IBL is expected to improve the b-tagging efficiency, help with pattern recognition performance and add tracking precision with respect to the current detector. Single and double chip modules are loaded on local mechanical support, in the form of 14 staves arranged in cylindrical barrel around the beam pipe. The production of the modules has already started, aiming for a total production of 24 staves including spares. Systematic Quality Assurance (QA) and Quality Control (QC) plans concerning modules, staves and flex from production to final assembly have been put in place. QA is performed in several collaborating institutes and final validation before installation in the ATLAS experiment will be carried out at CERN. Dedicated set-ups have been constructed in order to perform the full chain of QAlQC tests on the production staves. A CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cooling system is used to cool the pixel modules down to -35°C and an electronic chain similar to the final one has been developed. Furthermore a linear motion system carrying two 241 Am sources with an activity of 41 MBq each is mounted over the stave in order to perform a final characterization of the sensor's performance. The realization of source scans on the 24 production staves permits to analyze the response of sensors to radiation, to easily identify dead pixels, and to provide data for an eventual re-calibration of the charge calibration. The setup and first results obtained on prototype staves are described in detail.

Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

Silicon Sensor Technologies for the ATLAS IBL Upgrade

The ATLAS Insertable B-Layer (IBL) is the innermost layer of pixel detectors, and was installed in May 2014 at a radius of 3.3 cm from the beam axis, between the existing Pixel detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and occupancy, is the first large scale application of 3D sensors and CMOS 130 nm technology. The IBL detector construction was completed within about two years (2012 – 2014), and the key features and challenges met during the IBL project are presented, as well as its commissioning and operational experience at the LHC.

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.

The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the low-voltage current of the FE-I4 chip was measured. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionising Dose (TID) and temperature has been tested with X-ray irradiations. This paper presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration for the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. The HV-CMOS technology is a commercial integrated circuit process with the advantages of monolithic readout and fast charge collection. A front-end test platform of CaRIBOu (Control and Readout Itk BOard) and a testbeam Telescope based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, have been developed for the HV-CMOS sensor study and characterization in testbeam experiments. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between detector front-end electronics and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for both the CaRIBOu and the testbeam Telescope. It has been deployed successfully in the testbeam at the CERN SPS H8 beamline in August 2017. The test results show that the readout system is capable of sensor calibration and readout of a high-density pixel detector with high trigger rate in testbeam experiments.

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

The Compact Muon Solenoid (CMS) is a general purpose detector at the Large Hadron Collider (LHC). The LHC luminosity is constantly increased through upgrades of the accel- erator and its injection chain. Two major upgrades will take place in the next years. The rst upgrade involves the LHC injector chain and allows the collider to achieve a luminosity of about 2 10 34 cm-2 s-1 A further upgrade of the LHC foreseen for 2025 will boost its luminosity to 5 10 34 cm-2 s1. As a consequence of the increased luminosity, the detectors need to be upgraded. In particular, the CMS pixel detector will undergo two upgrades in the next years. The rst upgrade (phase I) consists in the substitution of the current pixel detector in winter 2016/2017. The upgraded pixel detector will implement new readout elec- tronics that allow ecient data taking up to a luminosity of 2 10 34 cm-2s-1,twice as much as the LHC design luminosity. The modules that will constitute the upgraded detector are being produced at dierent institutes. Hamburg (University and DESY) is responsible for the production of 350 pixel modules. The second upgrade (phase II) of the pixel detector is foreseen for 2025. The innermost pixel layer of the upgraded detector will accumulate a radiation damage corresponding to an equivalent uence of eq = 2 10 16 cm-2 and a dose of 10 MGy after an integrated luminosity of 3000 fb-1. Several groups are investigating sensor designs and congurations able to withstand such high doses and uences. This work is divided into two parts related to important aspects of the upgrades of the CMS pixel detector. For the phase I upgrade, a setup has been developed to provide an absolute energy calibration of the pixel modules that will constitute the detector. The cali- bration is obtained using monochromatic X-rays. The same setup is used to test the buering capabilities of the modules' readout chip. The maximum rate experienced by the modules produced in Hamburg will be 120 MHz/cm 2 . For this rate the modules' eciency has been measured to be 99%. In view of the module production, the energy calibration procedure has been automated. The modules assigned to the Hamburg production center should be completed by the end of February 2016. For the phase II upgrade, thin silicon sensors with an active thickness of 100 m irradi- ated with protons up to eq = 1 : 3 10 16 cm-2 have been characterized. The charge collection eciency has been measured using pad diodes. Charge multiplication eects have been ob- served for both n- and p-bulk sensors. P-bulk strip sensors with an active thickness of 100 and 200 m have been characterized with a beam test. The signal of these sensors lies be- tween 4000 and 5000 e- after a uence of 1 : 3 10 16 cm-2. The 200 m thick sensors require a higher bias voltage than the 100 m thick sensors to reach this signal height. The threshold necessary to obtain 95% detection eciency is found to be around 2000 e- for the 100 m thick sensors

The ATLAS collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

In this paper we report on the most recent achievements of the ATLAS 3D Sensors Collaboration in the development of silicon 3D sensors. Results from 3D pixels production for the ATLAS Insertable B-Layer (IBL) are presented, showing the high quality and good process reproducibility of the technology. In view of the future detector upgrades at the LHC, a new generation of 3D pixel sensors will be developed. This will require some new ideas and the solution of technological challenges. Both will briefly be addressed in this paper.

We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.