Silicon Sensor Technologies for the ATLAS IBL Upgrade

The ATLAS collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

In this paper we report on the most recent achievements of the ATLAS 3D Sensors Collaboration in the development of silicon 3D sensors. Results from 3D pixels production for the ATLAS Insertable B-Layer (IBL) are presented, showing the high quality and good process reproducibility of the technology. In view of the future detector upgrades at the LHC, a new generation of 3D pixel sensors will be developed. This will require some new ideas and the solution of technological challenges. Both will briefly be addressed in this paper.

The ATLAS Insertable B-Layer (IBL) is the innermost layer of pixel detectors, and was installed in May 2014 at a radius of 3.3 cm from the beam axis, between the existing Pixel detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and occupancy, is the first large scale application of 3D sensors and CMOS 130 nm technology. The IBL detector construction was completed within about two years (2012 – 2014), and the key features and challenges met during the IBL project are presented, as well as its commissioning and operational experience at the LHC.

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system.This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.

A multi-channel PCI express readout board for fast readout of large pixel detectors

During the first LHC long shutdown (2013/14) a new innermost pixel layer will be added to the present ATLAS Pixel Detector. The Insertable B-Layer (IBL) is a high-reliability, ultra light and radiation hard Pixel Detector assembled with 3D n-in-p and planar n-in-n pixel sensors. Facing the effects of increased luminosity and radiation damage, IBL is expected to improve the b-tagging efficiency, help with pattern recognition performance and add tracking precision with respect to the current detector. Single and double chip modules are loaded on local mechanical support, in the form of 14 staves arranged in cylindrical barrel around the beam pipe. The production of the modules has already started, aiming for a total production of 24 staves including spares. Systematic Quality Assurance (QA) and Quality Control (QC) plans concerning modules, staves and flex from production to final assembly have been put in place. QA is performed in several collaborating institutes and final validation before installation in the ATLAS experiment will be carried out at CERN. Dedicated set-ups have been constructed in order to perform the full chain of QAlQC tests on the production staves. A CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cooling system is used to cool the pixel modules down to -35°C and an electronic chain similar to the final one has been developed. Furthermore a linear motion system carrying two 241 Am sources with an activity of 41 MBq each is mounted over the stave in order to perform a final characterization of the sensor's performance. The realization of source scans on the 24 production staves permits to analyze the response of sensors to radiation, to easily identify dead pixels, and to provide data for an eventual re-calibration of the charge calibration. The setup and first results obtained on prototype staves are described in detail.

We report on the design and TCAD simulations of planar active-edge pixel sensors within the INFN PixFEL project. These devices are intended as one of the building blocks for the assembly of a multilayer, four-side buttable tile for X-ray imaging applications in future Free Electron Laser facilities. The requirements in terms of very wide dynamic range and tolerance to extremely high ionizing radiation doses call for high operation voltages. A comprehensive TCAD simulation study is presented, aimed at the best trade-offs between the minimization of the edge region size and the sensor breakdown voltage.

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration for the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. The HV-CMOS technology is a commercial integrated circuit process with the advantages of monolithic readout and fast charge collection. A front-end test platform of CaRIBOu (Control and Readout Itk BOard) and a testbeam Telescope based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, have been developed for the HV-CMOS sensor study and characterization in testbeam experiments. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between detector front-end electronics and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for both the CaRIBOu and the testbeam Telescope. It has been deployed successfully in the testbeam at the CERN SPS H8 beamline in August 2017. The test results show that the readout system is capable of sensor calibration and readout of a high-density pixel detector with high trigger rate in testbeam experiments.

The High Luminosity LHC upgrade demands enhanced tracking, prompting a complete replacement of ATLAS's Inner Detector with the all-silicon Inner Tracker (ITk). Spanning 33–291 mm from the beam pipe, ITk will use hybrid pixel detectors with 65 nm CMOS chips. The inner region, facing extreme radiation, will feature 3D pixel sensors due to their superior radiation tolerance, while the outer regions will use planar sensors. The production of 3D sensors is distributed among two vendors, FBK and SINTEF. The ITk linear triplet module consists of three hybrids (readout chip bump-bonded to a 3D pixel sensor) mounted on a flexible PCB. Extensive testing has been carried out on a linear triplet module in 2025 at CERN's test beam facilities, using 120 GeV pion beams to validate its performance under HL-LHC conditions. The most recent results of the module studied after irradiation will be presented here.

Various structures for n-in-p planar pixel sensors have been developed at KEK in order to cope with the huge particle fluence in the upcoming LHC upgrades. Performances of the sensors with different structures have been evaluated with testbeam. The n-in-p devices were connected by bump-bonding to the ATLAS Pixel front-end chip (FE-I4A) and characterized before and after the irradiation to 1×1016 1MeV neq/cm2. Results of measurements with 120GeV/c momentum pion beam at the CERN Super Proton Synchrotron (SPS) in September 2012 are presented.

An upgrade program is underway to increase the luminosity of the LHC up to about 7.5×1034 cm−2s−1 in 2027, with the goal of an integrated luminosity of 3000 fb−1 by the end of 2037. This High Luminosity scenario, HL-LHC, presents new challenges of higher data rates and increased radiation hardness for the pixel detector: a non-ionizing fluence of 2.3×1016 neq/cm2 an ionizing dose of 12 MGy, is expected on the inner pixel layer for 3000 fb−1 integrated luminosity. To maintain or even improve the performance of the present system, new technologies have to be fully exploited for the so-called Phase-II upgrade. Among them is the future version of front-end chips in 65-nm CMOS by the CERN RD53 Collaboration which supports small pixel sizes of 50×50 or 25×100 μm2 lower thresholds (∼ 1000 e−). For the development of the appropriate planar pixel sensor, CMS has recently launched a submission of n+-p sensors on 6 inch wafers with an active thickness of 150 μm at Hamamatsu. The submission consists of physically thinned, directly bonded and deep diffused wafers with p-stop or p-spray isolation. A variety of sensors with and without biasing scheme is designed to match the different read-out chips (RD53A, ROC4Sens, etc.) and first hybrid modules are assembled at Fraunhofer IZM. In this document, we will present an overview of the Phase II pixel R&D program and report on preliminary results on the HPK submission.

3D trenched-electrode pixel sensors: Design, technology and initial results

The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) to start operation in 2026. The most severe challenges are to be faced by the innermost layers of the pixel detector which will have to withstand a radiation fluence of up to 1.4×1016 n eq /cm2. Thin planar pixel modules are promising candidates to instrument these layers, thanks to the small material budget and their high charge collection efficiency after irradiation. Sensors of 100-200 μm thickness, interconnected to FE-I4 read-out chips, are characterized with radioactive sources as well as testbeams at the CERN-SPS and DESY. The performance of sensors irradiated up to a fluence of 5 × 1015 n eq /cm2 is compared in terms of charge collection and hit efficiency. Highly segmented sensors are a challenge for the tracking in the forward region of the pixel system at the HL-LHC. To reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidities, FE-I4 compatible planar pixel sensors are studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shape and hit efficiency will be shown.

The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.