The ATLAS Insertable B-Layer: from construction to operation

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system.This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration for the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. The HV-CMOS technology is a commercial integrated circuit process with the advantages of monolithic readout and fast charge collection. A front-end test platform of CaRIBOu (Control and Readout Itk BOard) and a testbeam Telescope based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, have been developed for the HV-CMOS sensor study and characterization in testbeam experiments. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between detector front-end electronics and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for both the CaRIBOu and the testbeam Telescope. It has been deployed successfully in the testbeam at the CERN SPS H8 beamline in August 2017. The test results show that the readout system is capable of sensor calibration and readout of a high-density pixel detector with high trigger rate in testbeam experiments.

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

During the first LHC long shutdown (2013/14) a new innermost pixel layer will be added to the present ATLAS Pixel Detector. The Insertable B-Layer (IBL) is a high-reliability, ultra light and radiation hard Pixel Detector assembled with 3D n-in-p and planar n-in-n pixel sensors. Facing the effects of increased luminosity and radiation damage, IBL is expected to improve the b-tagging efficiency, help with pattern recognition performance and add tracking precision with respect to the current detector. Single and double chip modules are loaded on local mechanical support, in the form of 14 staves arranged in cylindrical barrel around the beam pipe. The production of the modules has already started, aiming for a total production of 24 staves including spares. Systematic Quality Assurance (QA) and Quality Control (QC) plans concerning modules, staves and flex from production to final assembly have been put in place. QA is performed in several collaborating institutes and final validation before installation in the ATLAS experiment will be carried out at CERN. Dedicated set-ups have been constructed in order to perform the full chain of QAlQC tests on the production staves. A CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cooling system is used to cool the pixel modules down to -35°C and an electronic chain similar to the final one has been developed. Furthermore a linear motion system carrying two 241 Am sources with an activity of 41 MBq each is mounted over the stave in order to perform a final characterization of the sensor's performance. The realization of source scans on the 24 production staves permits to analyze the response of sensors to radiation, to easily identify dead pixels, and to provide data for an eventual re-calibration of the charge calibration. The setup and first results obtained on prototype staves are described in detail.

The ATLAS collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

Silicon Sensor Technologies for the ATLAS IBL Upgrade

A multi-channel PCI express readout board for fast readout of large pixel detectors

Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

In this paper we report on the most recent achievements of the ATLAS 3D Sensors Collaboration in the development of silicon 3D sensors. Results from 3D pixels production for the ATLAS Insertable B-Layer (IBL) are presented, showing the high quality and good process reproducibility of the technology. In view of the future detector upgrades at the LHC, a new generation of 3D pixel sensors will be developed. This will require some new ideas and the solution of technological challenges. Both will briefly be addressed in this paper.

The high luminosity phase of the Large Hadron Collider (HL-LHC) requires a major pixel detector R&D effort to develop both readout chip and sensor that are capable to withstand unprecedented extremely high radiation. The target integrated luminosity of 3000 fb−1, that the HL-LHC is expected to deliver over about 10 years of operation, translates into a hadron fluence of 2×1016 1 MeV eq.n. / cm2, or equivalently 10 MGy of radiation dose in silicon, at about 3 cm from the interaction region where the first layer of the pixel detector could be located. The CMS collaboration has undertaken two baseline sensor R&D programs on thin n-on-p planar and 3D silicon sensor technologies. Together with the ATLAS collaboration it has also been established a common R&D effort for the development of the readout chip in the 65 nm CMOS technology. Status, progresses, and prospects of the CMS R&D effort are presented and discussed in this article.

ALICE (A Large Ion Collider Experiment) is a general purpose heavy-ion experiment designed for the study of strongly-interacting matter at the extreme energy densities reached in Pb-Pb collisions at the CERN LHC, where the deconfined phase of hadronic matter known as Quark-Gluon Plasma (QGP), is formed. The innermost detector of ALICE is the Inner Tracking System. In its first release, it consists of six cylindrical layers of silicon detectors based on different technologies: two inner layers of pixel sensors (Silicon Pixel Detector), two intermediate layers of drift sensors (Silicon Drift Detector), two outer layers of strip sensors (Silicon Strip Detector). The ITS is used for the reconstruction of primary and secondary vertices, for particle tracking, for a precise determination of the impact parameter and for particle identification at low momentum. In this report, after a brief description of the three subdetectors, the operational experience with the first ITS implementation is summarized, the status and the performance of the detector are described and the lessons learned are discussed after the end of its operation coinciding with the completion of the LHC Run2.

The ATLAS Inner Detector consists of three layers of silicon pixel detectors, four double layers of silicon microstrip detectors and a straw tube based Transition Radiation Tracker. The good performance of the track and vertex reconstruction algorithms is a direct consequence of the small radius (4.3, 10.1 and 13.2 cm), fine pitch ( 50×300 μm ) and low occupancy (<3×10 −4 at design luminosity) of the pixel detectors, and of the good tracking capabilities of the silicon microstrip detector system and the transition radiation tracker. The full detector simulation is used to evaluate the performance of the detector and of the reconstruction algorithms. Results are presented on track and vertex reconstruction efficiencies and resolutions, and on the separation between b-jets and jets produced by light quarks.

ALICE, A Large Ion Collider Experiment, is conceived to study the physics of strongly interacting matter and the properties of the Quark–Gluon Plasma produced in ultra-relativistic heavy-ion collisions at the CERN LHC. The innermost detector of ALICE is the Inner Tracking System (ITS) which plays the essential role of primary and secondary vertex reconstruction. It is used for particle tracking and identification and contributes to the first level trigger. The ITS covers the pseudo-rapidity range |ƞ| < 0:9 and consists of six cylindrical layers of silicon detectors placed coaxially around the beam pipe. Three different technologies were selected to equip the ITS: pixel detectors for the two inner layers, drift detectors for the two central layers and strip detectors for the outer layers. In this report the three detectors constituting the ITS are briefly described, the operational experience during RUN2 is summarised with a focus on the performance of the detector compared to RUN1 and on the interventions done during the long technical stop at the end of 2015.