Scenarios and state machines

The notion of soft state has been introduced in packet-switched networks to achieve particular services for end-to-end communications, such as quality-of-service provisioning and configuration of stateful packet filters. Protocols built upon soft state principles were believed to be simple, however in practice they are far more complex. An important issue with such protocols is to ensure their operations to be error-free and deadlock-free. In the paper the use of formal techniques is proposed, specifically, Specification and Description Language (SDL) and Message Sequence Charts (MSCs), for modelling, analysis and validation of soft-state protocols. Based on a general state management system that identifies their most representative behaviour, an extensive study on modelling and validating soft-state protocols with SDL/MSCs is presented, and it is shown that design flaws and ambiguity introduced in informally specified, textual protocols can be avoided if a protocol is formally modelled.

Is open-edi a potential area for use of MSC and SDL?

The formal semantics of SDL-2000: Status and perspectives

Using the Unified Modeling Language (UML), static aspects at conceptual level are represented in structural diagrams such as class diagrams, while dynamic aspects are represented in behavioral diagrams such as state chart diagram, activity diagram, sequence diagrams and collaboration diagrams. And metric measures for those, improves the quality of design. The earlier work focuses on metrics for class diagrams. The main goal of this paper is to focus on the definition of mea -sures that applied to guarantee the validity of design through {NEntryA, NExitA, NA, NT, NS} State chart diagrams, {NM} Inter-action diagrams, and {NOA, NOUC, NOUCA}Use-Case diagrams. This measure of metric validates intrinsic understandability of all behavioral UML diagrams.KeywordsSoftware metricsUML behavioral diagramscomplexity metricstheoretical validation

SDL (Specification and Description Language) is an international standard formal description language which has been widely used for the specification and description of communication systems. SDL is based on the concept of the state oriented description technique—FSM (Finite State Machine). This paper reports an interactive generator for SDL, named SDL-TRAN, which can automatically translate FSM expression into SDL description. Except for its automatic translation part, SDL-TRAN includes an user-friendly graphical editor which is used to get the other part of SDL description which cannot be automatically translated.

UML activity and state chart diagrams are the most frequently UML models used for testing a system based on its specifications. Testers may choose different UML diagrams based on comprehensibility criteria. Previous studies, however, highlighted the lack of experts’ evaluation of comprehensibility of activity and state chart diagrams in test case generation. Thus, the main objective of this study is to evaluate the comprehensibility of the UML activity and state chart diagrams based on perspectives of experts. This study generated manual test cases from activity and state chart diagrams and used comprehensibility’s evaluation criteria during interviews with several software testing experts. The results of this study revealed that activity diagrams are more comprehensible than state chart diagrams in test case generation by considering comprehension variables (perceived difficulty and subjective confidence). The results of this study aim to unify the practical efforts of testers to choose MBT diagrams in generating test cases.

We present our approach to mixed hardware/software implementations of factory communication protocols. We start from a single system specification based on SDL (specification and description language). The main task consists of identifying the parts which when implemented in hardware would lead to the biggest gain in overall system performance. In order to achieve this we introduce a three stage solution. Within the first phase we use the environment dependence properties of control dominated systems to reduce the complexity of the next stages. Therefore we build a combined state machine from the existing CFSMs and identify the paths through it which are relevant to a speed up of the system. The second step exploits a new colouring algorithm in order to schedule the tasks of our program. In our case this means the SDL specification. This algorithm can be applied either to find the maximum degree of parallelism or to find the shortest schedule for a given number of parallel resources. The third step allocates the tasks to the system resources distributing the functionality between hardware and software elements. To exhibit the structural features of our approach we introduce SDL specification pictures if necessary.

The Unification of OMT, SDL and IDL for Service Creation

Statechart Diagrams are a notation for describing behaviours in the framework of UML, the Unified Modeling Language of object-oriented systems. UML is a semi-formal language, with a precisely defined syntax and static semantics but with an only informally specified dynamic semantics. UML Statechart Diagrams differ from classical statecharts, as defined by Harel, for which formalizations and results are available in the literature. This paper sets the basis for the development of a formal semantics for UML Statechart Diagrams based on Kripke structures. This forms the first step towards model checking of UML Statechart Diagrams. We follow the approach proposed by Mikk and others: we first map Statechart Diagrams to the intermediate format of extended hierarchical automata and then we define an operational semantics for these automata. We prove a number of properties of such semantics which reflect the design choices of UML Statechart Diagrams.KeywordsUnify Modeling LanguageOperational SemanticFormal SemanticComposite StateKripke StructureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Automating the process of test derivation from SDL specifications

Software performance concerns begin at the very outset of a new project. The first definition of a software system may be in the form of Use Cases, which may be elaborated as scenarios: this work creates performance models from scenarios. The Use Case Maps notation captures the causal flow of intended execution in terms of responsibilities, which may be allocated to components, and which are annotated with expected resource demands. The SPT algorithm was developed to transform scenario models into performance models. The UCM2LQN tool implements SPT and converts UCM scenario models to layered queueing performance models, allowing rapid evaluation of an evolving scenario definition. The same reasoning can be applied to other scenario models such as Message Sequence Charts, UML Activity Graphs (or Collaboration Diagrams, or Sequence Diagrams), but UCMs are particularly powerful, in that they can combine interacting scenarios and show scenario interactions. Thus a solution for UCMs can be applied to multiple scenarios defined with other notations.KeywordsCredit CardSequence DiagramLoop BodyLogical ResourceMessage Sequence ChartThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The interactive diagrams (ID) in the unified modeling language (UML) is consisted of object and the relation between objects, depicts the interaction relation and includes the information transferred between objects. As two interactive diagrams, the semantics of sequence diagrams (SD) and collaboration diagrams (CD) are equivalence in the unified modeling language, both diagrams can be converted with each other without the lost of information. But it is necessary that both diagrams coexist in the unified modeling language because their emphases are different in the course of interaction. Such study is instructive for practitioners to select both diagrams in real tasks.

In UML 2.0 sequence diagrams have been considerably extended, influenced by Live Sequence Charts (LSCs), a very expressive extension of Message Sequence Charts (MSC) with liveness. Nonetheless, fundamental liveness properties can still not be expressed in the new sequence diagrams. In recent work, we have proposed to solve this by enriching sequence diagrams with a simple but powerful Object Constraint Language (OCL) template for liveness. In this paper, we show how to formalize our liveness-enriched sequence diagrams using Abstract State Machines.

In testing systems with distributed interfaces/ports, we may place a separate tester at each port. It is known that this approach can introduce <it>controllability problems</it> which have received much attention in testing from finite state machines. Message sequence charts (MSCs) form an alternative, commonly used, language for modelling distributed systems. However, controllability problems in testing from MSCs have not been thoroughly investigated. In this paper, controllability problems in MSC test cases are analysed with three notions of observability: local, tester and global. We identify two types of controllability problem in MSC-based testing. It transpires that each type of controllability problem is related to a type of MSC pathology. <it>Controllability problems of timing</it> are caused by races but not every race causes controllability problems; <it>controllability problems of choice</it> are caused by non-local choices and not every non-local choice causes controllability problems. We show that some controllability problems of timing are avoidable and some controllability problems of choice can be overcome when testers have better observational power. Algorithms are provided to tackle both types of controllability problems. Finally, we show how one can overcome controllability problems using a coordination service with status messages based on algorithms developed in this paper.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.