Scheduling based energy optimization technique in multiprocessor embedded systems

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

Multi-core systems are now found in many electronic devices. But does current software design fully leverage their capabilities? The complexity of the hardware and software stacks in these platforms requires software optimization with end-to-end knowledge of the system. To optimize software performance, we must have accurate information about system behavior and time losses. Standard monitoring engines impose tradeoffs on profiling tools, making it impossible to reconcile all the expected requirements: accurate hardware views, fine-grain measurements, speed, and so on. Subsequently, new approaches have to be examined. In this article, we propose a non-intrusive, accurate tool chain, which can reveal and quantify slowdowns in low-level software mechanisms. Based on emulation, this tool chain extracts behavioral information (time, contention) through hardware side channels, without distorting the software execution flow. This tool consists of two parts. (1) An online acquisition part that dumps hardware platform signals. (2) An offline processing part that consolidates meaningful behavioral information from the dumped data. Using our tool chain, we studied and propose optimizations to MultiProcessor System on Chip (MPSoC) support in the Linux kernel, saving about 60% of the time required for the release phase of the GNU OpenMP synchronization barrier when running on a 64-core MPSoC.

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies based on task migration have been proposed to modulate power distribution between processing cores to achieve temperature flattening. However, in the context of MPSoC for multimedia streaming computing, where timeliness is critical, the impact of migration on quality of service must be carefully analyzed. In this paper we present the design and implementation of a lightweight thermal balancing policy that reduces on-chip temperature gradients via task migration. This policy exploits run-time temperature and load information to balance the chip temperature. Moreover, we assess the effectiveness of the proposed policy for streaming computing architectures by analyzing deadlines misses and architectural thermal effects of task migration using a cycle-accurate thermal-aware emulation infrastructure. Our results using a real-life software defined radio multitask benchmark show that our policy achieves thermal balancing while keeping migration costs bounded.

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in multiprocessor systems on chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies based on task migration have been proposed to modulate power distribution between processing cores to achieve temperature flattening. However, in the context of MPSoC for multimedia streaming computing, where timeliness is critical, the impact of migration on quality of service must be carefully analyzed. In this paper we present the design and implementation of a lightweight thermal balancing policy that reduces on-chip temperature gradients via task migration. This policy exploits run-time temperature and load information to balance the chip temperature. Moreover, we assess the effectiveness of the proposed policy for streaming computing architectures using a cycle-accurate thermal-aware emulation infrastructure. Our results using a real-life software defined radio multitask benchmark show that our policy achieves thermal balancing while keeping migration costs bounded.

Caches are used to bridge the gap between main memory and the significantly faster processor cores. In multi-core architectures, the last-level cache is often shared between cores. However, sharing a cache causes inter-core interference to emerge. Concurrently running tasks will experience additional cache misses as the competing tasks issue interfering accesses and trigger the eviction of data contained in the shared cache. Thus, to compute a task’s worst-case execution time (WCET), a safe bound on the effects of inter-core cache interference has to be determined. In this paper, we propose a novel analysis approach for shared caches using the least recently used (LRU) replacement policy. The presented analysis leverages timing information to produce tight bounds on the worst-case interference. We describe how inter-core cache interference may be expressed as a function of time using event-arrival curves. Thus, by determining the maximal duration between subsequent accesses to a cache block, it is possible to bound the inter-core interference. This enables us to classify accesses as cache hits or potential misses. We implemented the analysis in a WCET analyzer and evaluated its performance for multi-core systems containing 2, 4, and 8 cores using shared caches from 4 KB to 32 KB. The analysis achieves significant improvements compared to a standard interference analysis with WCET reductions of up to 60%. The average WCET reduction is 9% for dual-core, 15% for quad-core, and 11% for octa-core systems. The analysis runtime overhead ranges from a factor of 4 × to 7 × compared to the baseline analysis.

The theory and prior experimental studies for the high pressure shock compaction of porous metals are reviewed. The Mie-Gruneisen and Constant Derivative Mie-Gruneisen equations of state are not accurate for materials of high initial porosity shocked to high pressures. The equation of state proposed by Oh and Persson for these highly porous materials reduces the Gruneisen parameter of high internal energy states. The Oh-Persson equation of state does not predict the larger volumes at higher shock pressures known to exist for material of low initial porosity. We have modified the Oh-Persson equation of state by using an approximate Oh-Persson equation of state that has two asymptotes: the Mie-Gruneisen constant at low energy states and 0.5 at high energy states. The equation of state was applied to porous tungsten and compared with experimental data from the literature and other equations of state. The proposed equation of state shows improved correlation to experimental data for tungsten with high initial porosity, and reflects the larger volumes at high shock pressures for materials with low initial density. This is achieved while maintaining the close correlation to data obtained by most equations of state at higher initial densities.

Multiprocessor systems on chips (MPSoCs) are envisioned as the future of embedded platforms such as game-engines, smart-phones and palmtop computers. One of the main challenge preventing the widespread diffusion of these systems is the efficient mapping of multitask multimedia applications on processing elements. Dynamic solutions based on task migration has been recently explored to perform run-time reallocation of task to maximize performance and optimize energy consumption. Even if task migration can provide high flexibility, its overhead must be carefully evaluated when applied to soft real-time applications. In fact, these applications impose deadlines that may be missed during the migration process. In this paper we first present a middleware infrastructure supporting dynamic task allocation for NUMA architectures. Then we perform an extensive characterization of its impact on multimedia soft real-time applications using a software FM Radio benchmark.

Run-time task migration in a heterogeneous multiprocessor system-on-chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migration, minimization of the overhead during normal task execution (i.e., when not migrating) and the minimization of the migration reaction time are important. We introduce a novel technique that reuses the processor's debug registers in order to minimize the overhead during normal execution. This paper explains our task migration proof-of-concept setup and compares it to the state-of-the art. By reusing existing hardware and software functionality our approach reduces the run time overhead.

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and cooling. Hence, mechanisms to efficiently evaluate the effectiveness of advanced thermal-aware operating-system (OS) strategies (e.g. task migration) onto the available MPSoC hardware are needed. In this paper, we propose a new MPSoC OS emulation framework that enables the study of thermal management strategies at the architectural- and OS-levels with the help of a standard FPGA. This framework includes the hardware and software components needed to accurately model complex MPSoCs architectures, and to test the effects of run-time thermal management strategies at the OS/middleware level with real-life inputs. Our results show that migration overhead is negligible w.r.t. temperature timings, enabling the development of thermal-aware migration strategies. Moreover, the effectiveness of the monitoring and feedback mechanism provides an emulation performance only ten times slower than real time.

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised. This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.

Locking cache lines in hard real-time systems is a common means of achieving predictability of cache access behavior and tightening as well as reducing worst case execution time, especially in a multitasking environment. However, cache locking poses a challenge for multi-core hard real-time systems since theoretically optimal scheduling techniques on multi-core architectures assume zero cost for task migration. Tasks with locked cache lines need to proactively migrate these lines before the next invocation of the task. Otherwise, cache locking on multi-core architectures becomes useless as predictability is compromised. This paper proposes hardware-based push-assisted cache migration as a means to retain locks on cache lines across migrations. We extend the push-assisted migration model with several cache migration techniques to efficiently retain locked cache lines on a bus-based chip multi-processor architecture. We also provide deterministic migration delay bounds that help the scheduler decide which migration technique(s) to utilize to relocate a single or multiple tasks. This information also allows the scheduler to determine feasibility of task migrations, which is critical for the safety of any hard real-time system. Such proactive migration of locked cache lines in multi-cores is unprecedented to our knowledge.

Multi-processors systems-on-chip (MPSoCs) are becoming increasingly popular in embedded systems for the high degree of performance and flexibility they permit. While most MPSoCs are today highly heterogeneous for better fitting the target applications, homogeneous systems may become in a near future a viable alternative bringing other benefits such as run-time load balancing. The work presented in this paper relies on a homogenous NoC-based MPSoC framework we developed which allows us to conduct evaluations of 3 different techniques: proactive/reactive communication, preemptive task mapping and task replication. The impact on the system performance is discussed for several mappings of a MJPEG decoder application.

The concepts involved in the programming process of multicore systems have been quite well known for decades. The problem is to produce it in a form as easy as sequential programming. This new trend will change the way we think about the whole development process. We will show that it is possible to develop a multicore embedded system application using existing tools and the model-driven development process proposed. To do this, two tools will be used: VisualRTXC (available at www.quadrosbrasil.com.br) for generating the multithread communication/synchronization structures and a performance tool called TAU (available at http://www.cs.uoregon.edu/research/tau/home.php) for the tuning of the final implementation.

Shared last level cache has been widely used in modern multicore processors. However, uncontrolled cache sharing on multicore leads to more serious cache pollution than that on single-core processor. A process with weak locality can evict strong locality data sets that belong to other concurrent ones. Processes in multiprocessing environment always affect each other on multicore systems with shared last level cache. Prior approaches either partition shared cache in process level to reduce inter-process cache contention, or isolate the non-temporal memory accesses in order to accelerate single application execution. Process-based cache partitioning may make intra-process cache pollution more serious and have great impact on single process performance. In this work, we take an alternative view to explore physical page layout optimization by combining process-based cache partitioning and pollute region isolation for improving the shared last level cache utilization on multicore systems. Our proposed approach includes three steps. The first step determines the cache sizes of co-scheduled applications and the second step recognizes weak-locality regions of each application on different cache size configurations. Lastly, the third step customizes the physical page layout to partition cache space among concurrent processes and set up global pollute buffer for mapping pollute regions into a small slice of shared last level cache. Our approach is directly used in commercial multicore systems without any additional hardware requirement. Our experimental results show that in comparison with default Linux memory management scheme, our approach improves performance by 26.73% on average. Even compared to the process-based cache partitioning RapidMRC, our approach further eliminates the harmful effect of non-reusable data, and system performance is also improved by 5.63% on average.

With the rapid development of multi-core processor technology, parallelization has become the main approach for modern applications to improve throughput and responsiveness. However, the increasing number of processors also poses a challenge to the scalability of parallel program performance. In a traditional single-threaded program, all data is exclusively occupied by one thread, so the performance optimization of the program mainly focuses on the algorithm logic and implementation skills of the program; while in the multi-core system environment, most multi-threaded applications have performance scalability bottleneck. That is, the application cannot make full use of the performance advantages of multiple cores, and its performance decreases as the number of processors increases. The key factor restricting the improvement of performance scalability is often the synchronization mechanism of multi-core systems. Reader-writer lock is a synchronization mechanism that divides the operation to access shared resources or data into reader lock and writer lock, which enables effective cooperation between multiple different threads and ensures that applications can operate in a multicore environment with logical consistency. However, from another perspective, the reader-writer lock mechanism also limits the scalability of concurrent execution of applications. In application scenarios with different reader/writer ratios, the performance of reader-writer locks also differs, restricting the scalability of the performance of applications in multicore systems. Therefore, in a multi-core environment, it is of practical significance to implement a new type of readerwriter lock with scalable performance. This new reader-writer lock may automatically adjust the lock acquisition path according to the read/write ratio of the application scenario. In view of the shortcomings of the current reader-writer locks, this paper proposes a simple, efficient, optimized, and easy-to-implement adaptive reader-writer lock mechanism and interface which is suitable for multi-core environments, as well as application scenarios with different read/, write ratios. This mechanism gives full play to the high performance of multi-core systems and automatically adjusts lock acquisition according to different application scenarios. There are only minor changes to the application by replacing the original reader-writer lock instance and API interface function calls with an adaptive reader-writer lock instance and the API interface function calls for the adaptive reader-writer lock. The mechanism enables good scalability and improves the concurrency and scalability of reader-writer locks in multi-core systems in application scenarios with different read/write ratios. It will be conducive to meeting the growing demand for low latency, high throughput, and high concurrency processors.