Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in multiprocessor systems on chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies based on task migration have been proposed to modulate power distribution between processing cores to achieve temperature flattening. However, in the context of MPSoC for multimedia streaming computing, where timeliness is critical, the impact of migration on quality of service must be carefully analyzed. In this paper we present the design and implementation of a lightweight thermal balancing policy that reduces on-chip temperature gradients via task migration. This policy exploits run-time temperature and load information to balance the chip temperature. Moreover, we assess the effectiveness of the proposed policy for streaming computing architectures using a cycle-accurate thermal-aware emulation infrastructure. Our results using a real-life software defined radio multitask benchmark show that our policy achieves thermal balancing while keeping migration costs bounded.

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

Multiprocessor systems on chips (MPSoCs) are envisioned as the future of embedded platforms such as game-engines, smart-phones and palmtop computers. One of the main challenge preventing the widespread diffusion of these systems is the efficient mapping of multitask multimedia applications on processing elements. Dynamic solutions based on task migration has been recently explored to perform run-time reallocation of task to maximize performance and optimize energy consumption. Even if task migration can provide high flexibility, its overhead must be carefully evaluated when applied to soft real-time applications. In fact, these applications impose deadlines that may be missed during the migration process. In this paper we first present a middleware infrastructure supporting dynamic task allocation for NUMA architectures. Then we perform an extensive characterization of its impact on multimedia soft real-time applications using a software FM Radio benchmark.

Embedded System plays a vital role in consumer Industry. Complex applications need systems which contains multiple heterogeneous processors, running in parallel to speed up the system. Also due to area constraints, the processors are evolved in a single System on Chip called Multiprocessor System on Chip (MPSoC). The system should be reusable and debuggable, hence the designers designed and developed Reconfigurable MPSoCs rather than Application Specific Integrated Circuits (ASIC) in Field Programmable Gate Arrays (FPGA). Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However the growth of number of processing elements in one chip, task decomposition and scheduling become major bottlenecks of MPSoC architecture. To execute the applications, the application software is splitted as tasks and mapped to the different available processors and scheduled the tasks as when to execute in the available processors when the resources are ready. Selection of most suitable candidates for execution in a particular processor is very much important. Hardware related tasks are executed in different hardware accelerators and software tasks in processors. The area occupied by the schedulers in memory is more in internal memory. For scheduling these tasks, a programmable hardware is developed as hardware scheduler in the reconfigurable MPSoC using NIOS II processor. The algorithm for optimized scheduling in the target architecture is proposed. The literature survey is made with the hardware scheduler and new target MPSoC architecture. Quartus II version 12.1 and SOPC Builder are used to configure the NIOS II processer. Nios II EDS software tool has been used to build the application code.

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and cooling. Hence, mechanisms to efficiently evaluate the effectiveness of advanced thermal-aware operating-system (OS) strategies (e.g. task migration) onto the available MPSoC hardware are needed. In this paper, we propose a new MPSoC OS emulation framework that enables the study of thermal management strategies at the architectural- and OS-levels with the help of a standard FPGA. This framework includes the hardware and software components needed to accurately model complex MPSoCs architectures, and to test the effects of run-time thermal management strategies at the OS/middleware level with real-life inputs. Our results show that migration overhead is negligible w.r.t. temperature timings, enabling the development of thermal-aware migration strategies. Moreover, the effectiveness of the monitoring and feedback mechanism provides an emulation performance only ten times slower than real time.

Verification of softwarehardware hybrid systems is difficult because of the inter process communication, concurrency and synchronization and the configuration of processors. Multi-Processor Systems on Chip (MPSoC) are examples of such hybrid systems, targeted for embedded systems. We focus on the verification of MPSoC software (application running on MPSoC) and the system consisting of the application running on the MPSoC platform. We aim at generating test cases for verifying the software while overcoming the limitations of previous approaches. Metaheuristic approaches get blocked in local optima and constraint programming approaches are slow on complex programs, to satisfy given coverage criteria. We propose to combine metaheuristic and constraint programming solvers in a novel way: executing both the solvers sequentially and splitting and reducing the individual input variable domains. We also propose to generate test cases from the functional test objectives to check the proper functioning of the software running on the hardware platform. We report the results of the preliminary experiments.

본 논문은 MPI 집합 통신 함수가 처리 레벨 (transaction level) 에서 변환된다는 가정 하에 MPI 집합 통신 중 방송 (Broadcast), 확산 (Scatter), 취합 (Gather) 함수를 최적화한 알고리즘을 제안하였다. 또한 제안하는 알고리즘이 구동되는 MPI 전용 하드웨어 엔진을 설계하였으며, 이를 OCC-MPE (Optimized Collective Communication - Message Passing Engine) 라 명명하였다. OCC-MPE는 표준 송신 모드 (standard send mode)로 점대점 통신 (point-to-point communication) 을 하며, 집합 통신 중 가장 빈번하게 사용되는 방송, 취합, 확산을 제안하는 알고리즘에 의해 전송 순서를 결정한 후 통신하여 전체 통신 완료 시간을 단축시켰다. 제안한 알고리즘들의 성능을 측정하기 위하여 OCC-MPE를 SystemC 기반의 BFM(Bus Functional Model)을 제작하였다. SystemC 기반의 시뮬레이터를 통한 성능 평가 후에 VerilogHDL을 사용하여 제안하는 OCC-MPE를 포함한 MPSoC (Multi-Processor System on a Chip)를 설계하였다. TSMC 0.18 공정으로 합성한 결과 프로세싱 노드가 4개일 때 각 OCC-MPE가 차지하는 면적은 약 1978.95 이었다. 이는 전체 시스템에서 약 4.15%를 차지하므로 비교적 작은 면적을 차지함을 확인하였다. 본 논문에서 제안하는 OCC-MPE를 MPSoC에 내장하면, 비교적 작은 하드웨어 자원의 추가로 높은 성능향상을 얻을 수 있다. In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC <TEX>$0.18{\mu}m$</TEX>, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

Welcome to Sankt Goar and the SCOPES workshop. This year we are presenting a workshop program that features many interesting talks on all aspects related to the design of modern embedded systems. I hope that you will find our program interesting, stimulating and exciting. The influence of embedded systems is constantly growing. Increasingly powerful and versatile devices are developed and put on the market at a fast pace. Their functionality and number of features is increasing, and so are the constraints on the systems concerning size, performance, energy dissipation and timing predictability. To meet all these constraints, multi-processor systems on a chip (MPSoCs) are becoming popular in embedded systems. In order to meet the performance and energy constraints of embedded applications, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed. This technological trend has dramatic consequences on the parallelization, mapping, compiler and design technology used to develop these systems. The SCOPES workshop focuses on the software generation process for these modern embedded systems. Topics of interest include all aspects of the compilation and mapping process of embedded single and multiprocessor systems.

Run-time task migration in a heterogeneous multiprocessor system-on-chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migration, minimization of the overhead during normal task execution (i.e., when not migrating) and the minimization of the migration reaction time are important. We introduce a novel technique that reuses the processor's debug registers in order to minimize the overhead during normal execution. This paper explains our task migration proof-of-concept setup and compares it to the state-of-the art. By reusing existing hardware and software functionality our approach reduces the run time overhead.

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Growing complexity of multiprocessor systems on chip (MP-SoC) requires future communication resources that can only be met by highly scalable architectures. Networks-on-Chip (NoCs) offer this scalability and other advantages like modularity, quality-of-service (QoS), possibly smaller area footprint and lower power dissipation. Although many papers describe the advantages of NoCs and describe techniques to apply NoCs on certain application domains, few have actually employed the complete design chain to make a netlist level implementation and area comparison (Steenhof et al., 2006) and (Angiolini et al., 2006). This paper describes the application of the AEligthereal NoC to an existing bus-based MP-SoC design and an area comparison with the original interconnects structure down to netlist level

Distributed architectures with fixed-priority scheduling using Dynamic Power Management (DPM) for CPU optimization are one of the serious concerns in INTEL PXA270. Increasing the number of transistors and task mapping on chips causes greater energy dissipation and power consumption. This study addresses the issue of system-level higher CPU energy dissipation during the execution of parallel workloads with common deadlines by introducing a framework that includes task migration based on DPM and an Adaptive Deadline First scheduling (A-DF) scheme to properly schedule migratable tasks. The DPM policy and efficient task allocation and scheduling using A-DF enhance overall throughput and optimize energy consumption to avoid delays and performance degradation in multiprocessor systems. The proposed model assigns processors to the ready task set to meet deadline requirements. A full task migration policy is also integrated to ensure proper task mapping and interprocess linkage among tasks with the same deadlines. The execution of a task can pause on one CPU and reschedule execution on another to avoid delay and ensure that the deadline is met. The proposed method shifts the context of the task from running to sleep and from idle to sleep using an adaptive DPM approach. The proposed scheme showed a promising reduction in energy dissipation compared to other conventional energy-aware task migration techniques. Simulations were conducted using a super pipelined microarchitecture Intel XScale PXA270 using instruction and data cache per core of 32 Kbyte I-cache and 32 Kbyte D-cache on various utilization factors (ui) of 18% and 20%. The proposed approach consumed 6.3% less energy and achieved 2.1% and 2.4% improvements in terms of accuracy and precision when almost half of the CPU is running, and on a lower workload consumed 1.04% less energy. The proposed design provided significant improvements in clock rates of 100, 104, and 116 MHz.

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level Parallelism (DLP) partitioning. This architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

At the operating system level, multi-core and multiprocessor SoC(MPSoC) started a new computing era but brought various twofold scheduling challenges in current developed thermal aware algorithms for multi-core processors. An offline thermal aware scheduling algorithm is proposed for improvement in multi core embedded system in case of energy, reliability as well as performance of a multi core system has been introduced. Embedded systems are increasing at much rapid speed than ever before. The temperature of a multi-core processor is managed and measured by the hardware management system due to shrinking of chip size power densities are increasing due to this increase in the temperature of chip occurs that reduces the processor's speed in multi-core embedded system. High peak temperature on chip adversely affects the life span of chip. Task migration is a common technique to avoid peak temperature values in multi core system. Those tasks have been migrated in a multi core system which produces more heat to such individual core that has less temperature. The proposed technique also considers other thermal problems which affects the reliability and performance of multi-core system. In this research, a suitable scheduling mechanism assign tasks to the core that has less temperature by considering power and performance of the multi core system. This scheduling technique migrate load on the cores that is far away from the core reaches threshold temperature. For attaining stability in temperature among multiple cores results are evaluated by comparing different task migration techniques which are introduced previously. All types of hot and cold tasks are considered to predict accurate temperature by using thermal history. The scheduling policy attains maximum efficiency in terms of energy by considering only those cores that are executing some tasks in highest energy state such as running state while considering all other cores in lowest energy state such as sleep or a deep sleep mode. The simulation results shows that the proposed technique reduces almost 5°C temperature at 10% utilization and works efficiently when least number of tasks is in running state. The proposed technique has the ability to schedule more tasks to make a slower and energy efficient processor to control and manage the thermal effects on chip and also mange the processor energy consumption.

This paper is a try of contribution to explore and create embedded designs in the context of the MultiProcessor System on Chip (MPSoC) based on the state of the art Field Programmable Gate Array (FPGA), taking a case study and evaluation in the biomedical field. With this design approach, we have developed a Multiprocessor-based system for cardiac monitoring, with the Xilinx soft processor MicroBlaze. The Fast Simplex Link (FSL) bus is used as the mode of communication between the 3 MicroBlazes of this design. One processor is responsible of Human Machine Interface (HMI); another deals with Digital Signal Processing (DSP), and the third processor acts as the unique master that controls and coordinates the whole application software. Thus, the system permits, with success, the digitizing of the Electrocardiogram (ECG) analog signal, the displaying of heart rate (HR) on seven segments indicator, and the communication with a PC via the serial port for debugging and evaluation purposes. We have used the MIT-BIH Arrhythmia Database records to test and evaluate our implementation performance. The implementation occupies around 94% of the low-cost used FPGA, namely the Xilinx SPARTAN-6 XC6SLX16. The accuracy of the QRS detection, based on the well-known Pan and Tompkins algorithm, exceeds 96%.