Schottky Junction Vertical Channel GaN Static Induction Transistor with a Sub‐Micrometer Fin Width

A high-voltage normally-off AlGaN/GaN hybrid-gate HEMT (HG-HEMT) with high current-density and low on-resistance on Si substrate is fabricated. The proposed device features a hybrid-gate consisting of a short E-mode gate and a long D-mode gate. In the off-state, the short E-mode gate confirms the normally-off operation, while the D-mode gate can clamp the channel potential at a low drain voltage, which delivers high blocking capability. In the on-state, the short E-mode channel and the D-mode channel providing lower channel resistance facilitate high on-current or low on-resistance. Therefore, the HG-HEMT achieves a high breakdown voltage and low on-resistance simultaneously. Compared with the conventional device, the HG-HEMT is shown to deliver comparable breakdown voltage while featuring 62% lower on-resistance.

A superjunction GaN-based vertical heterojunction field effect transistor with ununiformly doped buffer (UDSJ-VHFET) is proposed in this paper. In contrast to the conventional superjunction vertical heterojunction field effect transistor (SJ-VHFET), the doping density of n-pillar increases linearly from top to bottom, while the p-pillar is split into three regions: linearly doped top region, uniformly doped middle region and linearly doped bottom region. The ununiform doping profile suppresses the increase of electric field peak due to the imbalanced charge and smooths the electric field distribution, thus leads to an increase of the breakdown voltage (Vbr) under charge imbalance condition. Simulation results show that with the doping dose of p-pillar 40% lower (higher) than that of the n-pillar, the Vbr and on-state resistance (Ron) of the proposed device are 6863 V and 4.25 mΩ cm2 (5751 V and 4.32 mΩ cm2), comparing with 3205 V and 4.03 mΩ cm2 (2175 V and 4.10 mΩ cm2) for the conventional SJ-VHFET. Additionally, the proposed device shows a Vbr of 12280 V and Ron of 4.29 mΩ cm2 under charge balance condition, comparing with 12874 V and 4.07 mΩ cm2 for the conventional SJ-VHFET.

Pseudomorphic growth of a UV-C laser diode heterostructure is demonstrated on a bulk AlN substrate by MBE. While stimulated emission is not observed under current injection, spontaneous emission at 265 nm is observed. Current densities up to 800 A/cm2, >5 orders on/off ratio at ±5 V, and a low differential on-resistance of 2.6 mΩ cm2 at the highest current density are achieved. The heterostructure has a high refractive index waveguide core surrounded by n- and p-cladding layers for mode confinement at 270 nm to facilitate edge emission and collection of photons. Edge-collection electroluminescence of the devices is achieved by cleaving the fabricated devices along the m-plane of the wurtzite crystal. Electrical injection results in the emission of high-energy 4.7 eV photons that are collected from the cleaved edge of the heterostructure, corresponding to the optical bandgap of the AlGaN active region. The contribution of power dissipation across the n- and p-regions of the diode is discussed. The n-contact resistance to n-AlGaN is identified as the largest contributor to the series resistance of these devices. Reduction of these resistances will allow these heterostructures to achieve lasing in the future.

4H-SiC is a promising material for low-loss, high frequency, and high temperature electronic devices. And nowadays, 4H-SiC Schottky diodes, MOSFETs, and its inverters were used in many applications. As well known, a conduction loss and a switching loss shows tread off relationship on these devices. Schottky diode shows high speed switching action and small recovery current based on its unipolar operation, but high series resistance of drift layer. On the other hand, PiN diode shows low series resistance of drift layer due to its conductivity modulation phenomenon based on the bipolar action. However, it causes an adverse reverse recovery current and limited switching speed. To break this tread off relationship, Schottky-PN diode structure so-called SPND or SNPD was proposed with a diamond semiconductor [1]. This diode has a structure with a low doped n- or p- drift layer where is sandwiched and completely depleted with Schottky junction and one side PN junction. Under forward bias condition, barrier height of PN junction is reduced and majority carrier was injected into the drift layer completely depleted with Schottky junction. Injected majority carrier drift to Schottky junction without recombining with minority carrier. It means minority carrier dose not contribute to current flow under forward bias. Then, this SPND structure is expected to show both very low on-resistance and high speed switching action. Under reverse bias condition, blocking voltage is shared throughout the drift layer. However, the diamond semiconductor material is under development and difficult to use production phase. In this study, we demonstrated the possibility of SPND by using 4H-SiC substrate under mass production. In this study, we grew low doped p-layer on n+ 4H-SiC C-face substrate by using hot-wall chemical vapor deposition (CVD) system with H2-SiH4-C3H8 gas system. Trimethylaluminum (TMA) was used as p-type dopant source. The thickness and doing concentration of grown p- layer is 1.1 μm and 5 x 1014 cm-3. Pt was evaporated in vacuum as Schottky electrode on as grown surface. The diameter of Schottky contact is 1mm. Al was used as ohmic back contact. The schematic cross-sectional structure of fabricated 4H-SiC SPND is shown inset of Figure 1. Figure 1 shows typical J-V characteristic of fabricated 4H-SiC SPND at room temperature. Good rectifying characteristic was observed. The blocking voltage of 300 V was obtained (Fig. 1(a)). From this result, we estimated dielectric breakdown field value of 2.5 MV/cm which is almost equal to ideal value of 4H-SiC one. On forward bias characteristic, the current raises at 2.2 V and the current density is reached at 1200 A/cm2 at 2.4 V (Fig. 1(b)). From this value, the differential on-resistance was estimated at 0.18 mΩcm2. In this study, we used 4H-SiC substrate with thickness of 200 μm and resistivity of 20 mΩcm. The calculated series on-resistance of 4H-SiC substrate part was estimated as 0.4 mΩcm2. This result means estimated differential on-resistance of 0.18 mΩcm2 is almost the resistance of substrate and the resistance of drift layer dose not contribute to the series resistance. These results mean 4H-SiC SPND structure was realized and its good performance of low on-resistance with high blocking voltage was confirmed. Details will be shown in this presentation.

Fluorine-free hydrocarbon polymers have the potential to be more environmentally friendly and cost-effective than current perfluorinated sulfonic acids (PFSA). These hydrocarbon polymers have a unique morphology that reduces gas transfer while maintaining high proton conductivity, making them a promising alternative to PFSA membranes in water electrolysis.[1] In an initial study, we demonstrate the potential of hydrocarbon membranes in electrolyzers using sulfonated polyphenylene sulfone (sPPS).[2] However, to achieve good performance, a high ion exchange capacity (2.17 - 3.57 meq/g) is required. This results in a high water uptake, which leads to membrane softening and detachment of the electrodes. In addition, excessive swelling makes upscaling, i.e., coating of the electrodes directly onto the membrane, impossible. To solve this problem, we have integrated a woven, open-mesh PEEK substrate (Fig.1, right).[3] The reinforced membrane shows a significant enhancement in the mechanical robustness and dimensional stability of the membrane, which leads to a strong reduction of water uptake from 294% to 115%. This allows direct casting of electrodes onto the membrane, an essential step for scaled production. Moreover, the reinforced membrane demonstrates a significantly lower electrical resistance of 70 mΩ cm² (versus 159 mΩ cm² for Nafion), attributed to its reduced thickness (74 µm compared to 127 µm) and higher ion exchange capacity. At the same time, the crossover is also strongly reduced as displayed in Figure 1. This leads to a better figure of merit, given by the ratio of conductivity to permeability, as shown in Figure 1 (right bottom), where crossover current densities are plotted over the high frequency resistance.[3] Figure 1Illustration of the casting Process of the reinforced membrane and fabrication of a one side coated CCM (left). IV-curve of the PEEK-sPPS membrane and a Nafion 115 reference (top right) and the figure of merit for PEEK-sPPS and two reference membranes (N115 and N212). Literature: [1] Miyake, J.; Taki, R.; Mochizuki, T.; Shimizu, R.; Akiyama, R.; Uchida, M.; Miyatake, K. Design of flexible polyphenylene proton-conducting membrane for next-generation fuel cells. Sci. Adv. 2017, 3(10), eaao0476. DOI: 10.1126/sciadv.aao0476[2] Klose, C.; Saatkamp, T.; Münchinger, A.; Bohn, L.; Titvinidze, G.; Breitwieser, M.; Kreuer, K.; Vierrath, S. All‐Hydrocarbon MEA for PEM Water Electrolysis Combining Low Hydrogen Crossover and High Efficiency. Adv. Energy Mater. 2020, 10 (14), 1903995. DOI: 10.1002/aenm.201903995[3] Qelibari, R.; Cruz Ortiz, E.; van Treel, N.; Lombeck, F.; Schare, C.; Münchinger, A.; Dumbadze. N.; Titvinidze, G.; Klose, C.; Vierrath, S. 74 µm PEEK-reinforced sulfonated poly(phenylene sulfone)-membrane for stable water electrolysis with lower gas crossover and lower resistance than Nafion N115. Adv. Energy Mater. 2023, 14 (5), 2303271. DOI: 10.1002/aenm.202303271 Figure 1

In this work, a novel GaN vertical junction field-effect transistor (JFET) with intrinsic reverse conduction capability (RC-JFET) is proposed and studied by simulation. The RC-JFET features two separate source electrodes, one of which performs as an embedded freewheeling diode that can enable the reverse conduction function of the device. Benefiting from a structure with two separate source electrodes, the forward and reverse current conduction paths are also separated, which allows us to independently design the forward and reverse conduction characteristics of the RC-JFET. The forward threshold voltage V TH is 1.6 V while the reverse turn-on voltage V on,rev is as low as 0.7 V. In addition, the buried floating p-base can effectively modulate the E-field in the GaN drift region, which can achieve a high breakdown voltage of 1720 V with an R on,sp of 2.79 mΩ cm2. Due to the embedded freewheeling diode, the device exhibits a short reverse recovery time T rr of 13 ns. By featuring an intrinsic reverse conduction capability, the proposed RC-JFET is capable of eliminating the externally connected diode, which is beneficial for improved switching speed and switching power loss due to the reduction of parasitic effects and chip size of power circuits.

Corrosion behavior of metallic coatings on titanium bipolar plates of proton exchange membrane water electrolysis

Output characteristics of a XeCl laser at very high discharge current density (j=14 kA cm-2) were studied experimentally. At an estimated electron number density of about 1*1016 cm-3, electron quenching did not dominate over XeCl* (B or C) formation. The XeCl active medium exhibits very high gain characteristics at high current density. High power laser output was extracted from the active volume and a volatile dependence on HCl partial pressure was observed. The rapid build-up of gain was attributed to fast excimer formation resulting from increased number of densities of ionic precursors (Xe+ and Cl-). Electron-HCl kinetics processes that contribute to the enhancement of the formation of atomic ions were also discussed.

We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

The SiC trenched-and-implanted vertical junction field-effect transistor (TI-VJFET) is an excellent device for power switching applications, but its on-resistance needs to be further reduced to suppress ON-state power loss. In this paper, we used small cell pitch size and high channel/drift layer doping concentration to achieve low on-resistance. Advanced fabrication processes, such as Bosch process trench etching, self-aligned Ni silicide, and self-aligned gate overlay were implemented to support such an aggressive design. Normally on 4H-SiC TI-VJFETs of various channel-opening dimensions have been designed and fabricated based on a 12 mum, 1.8 times 1016 cm-3 doped drift layer. Record high performance TI-VJFETs have been achieved and will be reported. Other SiC VJFET structures under active research are reviewed and compared to TI-VJFET. Without the need for epi-regrowth or stringent lithography alignment, TI-VJFET has the advantage of a less demanding fabrication process. In addition, its high current density, adjustable channel width and low gate resistance make TI-VJFET an excellent device for fast power switching applications.

GaN based power transistors have attracted intensive interest for highly efficient, high-frequency and high-temperature switching applications. Compared with GaN lateral devices, GaN based vertical devices can provide higher current density and higher breakdown voltage. In combination with low defect density offered by GaN substrates, GaN vertical transistors will fully exploit the great potential of GaN technology. We will present the recent developments in GaN vertical trench-gate MOSFETs and current aperture vertical electron transistors, with emphasis on our efforts to tackle some key challenges in MOS interface and leakage current. The performance of GaN vertical devices on GaN substrates will also be compared with that of GaN vertical devices on Si substrates.

It is generally accepted that dust resistivity in excess of $${10}^{11}\, \Omega {\rm cm}$$ leads to the formation of back corona and to a deterioration of ESP performance. Besides dust conditioning, the most popular approach for reducing problems with back corona is the application of pulsed corona systems. The idea behind pulsing is very simply to reduce the E-field within the dust layer by reducing the time-averaged current density. However, experience shows that other high resistivity cases are resolved successfully with an opposing approach, using especially smooth HV from three-phase rectifiers in combination with high current densities. A detailed investigation into this discrepancy has revealed that high values of dust resistivity can be traced back to at least two different mechanisms. “Standard” high resistivity dusts show the behaviour which is typical for dielectrics. High potential drop across the dust layer is produced by the injection and immobilization of charge carriers into the material. Resistivity is strongly dependent on time and corona polarity and inversely proportional to the root of current density. The dust layers reach a high level of space charge density. In a sample of an “untypical” high resistivity dust we found that resistivity is independent of layer thickness and of corona polarity and does not show time effects. The dust layer does not accumulate any significant amount of space charge. The potential drop across the dust layer is nearly independent from current density, resulting in a resistivity which is inversely proportional to current density. With very high E-fields, the dust layer shows a progressive increase of current uptake with time, ending in a breakthrough. All these are the typical characteristics of a varistor material. Our results show that different mechanisms of high dust resistivity do exist. Therefore an appropriate choice of the high voltage supply and its control should be based on a thorough analysis of the electrical properties of the dust. A clearly better separation efficiency will be achieved.

The present study aims (i) to examine the association of physical fitness components (i.e., cardiorespiratory fitness, speed-agility, and muscular fitness) with brain current source density during working memory; and (ii) to examine whether fitness-related current density was associated to working memory performance and academic achievement. Eighty-five children with overweight/obesity aged 8-11years participated in this cross-sectional study. Physical fitness components were assessed using the ALPHA test battery. Electroencephalography recordings were performed during a Delayed Non-Match-to-Sample task that assessed working memory. Brain source analysis was carried out using sLORETA to estimate regional current source density differences between high and low (H-L) working memory loads. Academic achievement was measured by the Spanish version of the Woodcock-Johnson III test battery. The main results showed that higher cardiorespiratory fitness was associated with higher H-L current density differences in frontal, limbic, and occipital regions during encoding and maintenance task's phases (β≥0.412, p≤0.019). A limbic area was further related to better working memory performance (β=0.267, p=0.005). During retrieval, higher cardiorespiratory fitness was also associated with higher current density in temporal regions (β=0.265, p=0.013), whereas lower muscular fitness was associated with higher current density in frontal regions (β=-0.261, p=0.016). Our results suggest that cardiorespiratory fitness, but not speed-agility nor muscular fitness, is positively associated with brain current source density during working memory processes in children with overweight/obesity. Fitness-related current density differences in limbic regions were associated with better working memory.

Boosting Electrocatalytic CO ₂ Reduction with Conjugated Bimetallic Co/Zn Polyphthalocyanine Frameworks

Silicon power MOSFETs have been used for a wide variety of electronic devices in many application fields. In order to obtain high breakdown voltage and low on-resistance, trench field-plate (FP) MOSFETs have been continuously developed in recent years. It is necessary to design deep trench and thick field-plate oxide for higher breakdown voltage FP-MOSFETs [1]–[6]. In state-of-the-art FP-MOSFETs, as shown in Fig. 1, high cell density design has been developed for the purpose of getting low on-resistance. Fundamentally, it needs to shrink cell pitch, which consists of trench width and mesa width. Forming vertical trench is one method to realize narrow cell pitch. Voids are, however, generated in source field-plate polysilicon or gate poly-silicon in general [7]. If voids are gathered widely at the bottom of the source field-plate polysilicon (Fig. 1(a)), the effect of field-plate such as high breakdown voltage and good device characteristics cannot be obtained properly. Furthermore, if voids are formed at the bottom edge of the gate poly-silicon (Fig. 1(b)), effective gate bottom edge is underlapped with p-base. Thus, it is difficult to form the channel inversion layer at gate oxide interface. As a result, the on-resistance becomes increased. Therefore, suppressing void generation is one of the most significant process controls for trench FP-MOSFETs.