Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications

Embedded System plays a vital role in consumer Industry. Complex applications need systems which contains multiple heterogeneous processors, running in parallel to speed up the system. Also due to area constraints, the processors are evolved in a single System on Chip called Multiprocessor System on Chip (MPSoC). The system should be reusable and debuggable, hence the designers designed and developed Reconfigurable MPSoCs rather than Application Specific Integrated Circuits (ASIC) in Field Programmable Gate Arrays (FPGA). Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However the growth of number of processing elements in one chip, task decomposition and scheduling become major bottlenecks of MPSoC architecture. To execute the applications, the application software is splitted as tasks and mapped to the different available processors and scheduled the tasks as when to execute in the available processors when the resources are ready. Selection of most suitable candidates for execution in a particular processor is very much important. Hardware related tasks are executed in different hardware accelerators and software tasks in processors. The area occupied by the schedulers in memory is more in internal memory. For scheduling these tasks, a programmable hardware is developed as hardware scheduler in the reconfigurable MPSoC using NIOS II processor. The algorithm for optimized scheduling in the target architecture is proposed. The literature survey is made with the hardware scheduler and new target MPSoC architecture. Quartus II version 12.1 and SOPC Builder are used to configure the NIOS II processer. Nios II EDS software tool has been used to build the application code.

Verification of softwarehardware hybrid systems is difficult because of the inter process communication, concurrency and synchronization and the configuration of processors. Multi-Processor Systems on Chip (MPSoC) are examples of such hybrid systems, targeted for embedded systems. We focus on the verification of MPSoC software (application running on MPSoC) and the system consisting of the application running on the MPSoC platform. We aim at generating test cases for verifying the software while overcoming the limitations of previous approaches. Metaheuristic approaches get blocked in local optima and constraint programming approaches are slow on complex programs, to satisfy given coverage criteria. We propose to combine metaheuristic and constraint programming solvers in a novel way: executing both the solvers sequentially and splitting and reducing the individual input variable domains. We also propose to generate test cases from the functional test objectives to check the proper functioning of the software running on the hardware platform. We report the results of the preliminary experiments.

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

Multiprocessor System-on-Chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding heterogeneous processing elements, e.g. massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. We investigate the benefits of a resource-aware programming model called Invasive Computing for dynamically mapping image processing applications to different types of PEs available on a heterogeneous MPSoC. A case study of visual object recognition is presented, including Harris corner detection and SIFT feature matching. Results indicate that resource-aware programming helps to predict the latency of the application program along with better overall workload distribution within the heterogeneous MPSoC.

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Inter-core communication introduces overheads in task schedules on Multiprocessor System-on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the timing performance but also significantly degrades the memory usage for streaming applications running on MPSoC architectures. By minimizing inter-core communication overhead, a shorter period can be applied and system performance (e.g., throughput, memory usage) can be improved. In this paper, we focus on solving the problem of minimizing inter-core communication overhead for streaming applications on bus-based MPSoCs. The objective is to minimize inter-core communication overhead while minimizing the overall memory usage. To solve the problem, we first let tasks with intra-period data dependencies transform to inter-period data dependencies so as to overlap the execution of computation and inter-core communication tasks. By doing this, inter-core communication overhead can be effectively removed. To minimize the overall memory usage, we then perform schedulability analysis and obtain the bounds of the times needed to reschedule each task. Based on the schedulability analysis, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal schedule. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on a set of benchmarks from both real-life streaming applications and synthetic task graphs. The experimental results show that the proposed approach can significantly reduce the schedule length and improve the memory usage compared with the previous work.

Efficient and precise simulation models at a high abstraction level are required in order to perform early design validations and architecture explorations of multi- processor system-on-chip (MPSoC) platforms. Although native software simulation approaches provide interesting capabilities, they quickly become unsuitable when complex hardware architecture have to be considered. In this paper, we present a SystemC-based MPSoC platform implementation that allows native software simulation while keeping details of the underlying hardware model. The key contribution of this work is a realistic memory mapping modelling that makes possible the simulation of operating systems and software applications on complex hardware models with multiple processors and DMA devices. This method also allows the reuse of different software components for the target processor(s). Experimental results show the efficiency of the proposed method to validate software on complex hardware architectures.

Network on Chip (NoC) has become a promising solution for the communication paradigm of the next-generation multiprocessor system-on-chip (MPSoC). As communication has become an integral part of on-chip computing, researchers are paying more attention to its implementation and optimization. Traditional techniques that model inter-processor communication inaccurately will lead to unexpected runtime performance, which is on average 90.8% worse than the predicted results based on an observation. In this paper, we present an application mapping and scheduling technique for NoC-based MPSoCs that integrates fine-grain optimization on inter-processor communications with the objective of minimizing the schedule length. A communication model is proposed to address properly the latency of inter-processor communication with network contention. Performance evaluation results show that solutions obtained by the proposed technique can generate realistic performance that is on average 34.7% higher than traditional techniques, and the Integer-Linear Programming (ILP) based approach can outperform the state-of-the-art heuristic algorithms by 31.1%. A case study on H.264 HDTV decoder shows that our approach achieves 22.8% improvement in prediction accuracy, 20.9% improvement in performance and 40% reduction in the number of network contentions.

The recent years have witnessed a variety of new embedded applications. Typical examples include mobile multimedia gadgets, digital televisions, high-end cell phones, wireless network applications, etc. The salient features of these applications include more comprehensive functionalities, higher performance demand, and low-power consumption. These requirements render the traditional single processor-based embedded systems no longer an appropriate realization for such applications. On the other hand, the continual advance of VLSI technologies enables more and more transistors to be integrated on a single chip. The International Technology Roadmap for Semiconductors predicts that chips with a billion transistors are within reach. As a result, the push (application demands) and pull (VLSI technology) forces together give birth to the multi-processor system-on-chips (MPSoCs).Heterogeneous MPSoCs are different from traditional embedded systems in many aspects and they ask for new design and implementation methodologies. Heterogeneous MPSoCs are not merely a hardware design. The complexity and heterogeneity of the system significantly increase the complexity of the HW/SW partitioning problem. Meanwhile, evaluating the performance and verifying its correctness is much more difficult compared to traditional single processor-based embedded systems. Constructing a simulator to simulate the system’s behavior and evaluate its performance takes more effort compared to conventional embedded systems. The verification of the system also becomes challenging.Programming a heterogeneous MPSoC is another challenge to be faced. This problem arises simply because there are multiple programmable processing elements and since they are heterogeneous, software designer needs to have expertise on all of these processing elements and needs to take a lot of care on how to make the software running as a whole.There are a lot more issues that do not appear or easier to tackle on traditional embedded systems, trade-offs between performance and low-power will dominate the design life time. However, the incoming challenges also brought us many opportunities either to industry and academic research.

The ever increasing performance gap between processors and memories is one of the biggest performance bottlenecks for computer systems. In this paper, we propose a task scheduling technique that schedules an application, modeled with a task graph, on a multiprocessor system-on chip (MPSoC) that contains a limited on-chip memory. The proposed scheduling technique explores the trade-off between executing tasks in a code-driven (i.e. executing parallel tasks) or data-driven (i.e. executing pipelined tasks) manner to minimize the run-time of the application. Our static scheduler identifies those task sequences in which it is useful to use a code-driven execution and those task sequences that benefit from a data-driven execution. We extend the proposed technique to consider prefetching when choosing a suitable task order. The technique is implemented using an integer linear programming framework. To evaluate the effectiveness of the technique, we use an application from the multimedia domain and a synthetic task graph that is used in related work. Our experimental results show that our scheduler is able to reduce the run-time of an MP3 decoder application by 8% compared to a commonly used heuristic scheduler.

Application-Specific Network-on-Chip synthesis with flexible router Placement

In nanometer technology regime, process variation (PV) causes uncertainties in the processor frequency and leakage power, affecting the overall performance and energy efficiency of Multi-Processor System-on-Chips (MPSoCs). Mostly, the Power and Performance Yield optimizations are not done simultaneously while scheduling the tasks at the system level. We demonstrate the significance of optimizing both Power and Performance Yields simultaneously in task scheduling in order to minimize the effects of process variation at the system level. In this paper, we present process variation aware task scheduling algorithms and define a new design metric, called Power-Performance Yield (PPY) to guide the scheduling procedure. The PPY is modeled considering the spatial correlation characteristic of systematic process variation, log-normal distributions of leakage power and an energy-aware slack budgeting approach. We propose a novel mathematical formulation using Mixed Integer Linear Programming (MILP) technique and also employ an improved Simulated Annealing (SA) based stochastic technique for PPY optimization. The experimental results on TGFF generated random task graphs and E3S benchmark suite demonstrate average PPY improvements of 16.9% and 31% over two other SA based schemes that separately optimize Performance Yield and Power Yield, respectively. With accurate PV-aware modeling, we obtain average PPY improvements of 9.65% and 30.3% under strong correlations and 12.9% and 29.8% under weak correlations when compared to two other existing scheduling schemes that lack appropriate modeling.

Streaming media applications represent an important class of applications for embedded systems. Recent advances in design-space exploration of architectures for such applications have pointed towards the suitability of Multiprocessor System on Chip (SoC) solutions. Multiprocessor SoCs not only offer higher performance, but can also lead to solutions which are cheaper cost wise. A typical synthesis methodology for such architectures would require a validation stage at the end of final system integration. The wide availability of cheap and large FPGA devices, advances in automatic synthesis from VHDL/Verilog and abundance of high performance computing platforms enables the design of a generic validation system for such Multiprocessor SoCs.In this paper we present the design and implementation of Srijan Multiprocessor Prototyping System (SMPS). SMPS is a system for rapid prototyping and validation of single chip application specific multiprocessor systems. The individual computing elements are RISC processors, coprocessors which lie in the processor pipeline, and ASICs which connect directly to system bus. The system is a tightly coupled multiprocessor with shared memory and shared address space. A Real-time Operating System (RTOS) provides task scheduling and access to shared resources. The system is presented as a parameterized VHDL based on the open source Sparc~V8 compliant LEON processor and a homegrown light-weight RTOS, RtKer-MP. The entire VHDL is configurable using a GUI, has support for cache coherency, choice of arbitration policy and easy integration of custom processing engines. RtKer-MP allows for a pluggable scheduler, dynamic and static scheduling policies, static and dynamic task migrations domains and variable interruption frequencies for separate processors. The pluggable scheduler interface allows for quick exploration of various scheduling policies for a feedback to the estimation systems.

The study of climate-relevant processes in the atmosphere using airborne platforms is an important contribution to understanding our environment. The deployment of remote sensing instruments on aircraft or balloons requires powerful computer systems for data acquisition and instrument control. The ongoing trend towards further miniaturisation of instruments, with increasingly complex measurement tasks and higher data rates for use over longer flight durations, requires a new generation of control and processing units. These units must be significantly reduced in mass, volume and power consumption. In addition, a shift in data management from storage and post-processing to real-time data processing is required to reduce the increasing amounts of data and to transmit them to ground stations.Based on years of experience with the GLORIA (Gimballed Limb Observer for Radiance Imaging of the Atmosphere) instrument and its current miniaturised version, GLORIA-Lite, a modular and reconfigurable data acquisition and processing platform has been developed. This platform is specifically designed to meet the demanding requirements of future long-duration flights in harsh environments, with significant optimisations in weight, volume and power consumption. Using state-of-the-art multi-processor system-on-chip (MPSoC) modules, the platform enables real-time data processing while significantly reducing the need for data storage or transmission. Redundancy in hardware and software using the multiple processor cores, together with a supervisor circuit, makes the platform ready for harsh environments. Thanks to its compact form factor, the ruggedised and fully reprogrammable hardware is adaptable to a wide range of applications, further enhancing its versatility and potential for use in various scientific and technological missions.This presentation will show the prototype of the new processing platform, which will be used together with the GLORIA-Lite instrument during an upcoming balloon campaign. First processing steps and performance analysis will be presented.

General purpose Gpus provide massive compute power, but are notoriously difficult to program. In this paper we present a complete compilation strategy to exploit Gpus for the parallelisation of sequential legacy code. Using hybrid data dependence analysis combining static and dynamic information, our compiler automatically detects suitable parallelism and generates parallel OpenCl code from sequential programs. We exploit the fact that dependence profiling provides us with parallel loop candidates that are highly likely to be genuinely parallel, but cannot be statically proven so. For the efficient Gpu parallelisation of those probably parallel loop candidates, we propose a novel software speculation scheme, which ensures correctness for the unlikely, yet possible case of dynamically detected dependence violations. Our scheme operates in place and supports speculative read and write operations. We demonstrate the effectiveness of our approach in detecting and exploiting parallelism using sequential codes from the Nas benchmark suite. We achieve an average speedup of 3.2x, and up to 99x, over the sequential baseline. On average, this is 1.42 times faster than state-of-the-art speculation schemes and corresponds to 99% of the performance level of a manual Gpu implementation developed by independent expert programmers.