Sequential circuit test generation on a distributed system

An efficient sequential circuit test generation algorithm is presented. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of an initial time-frame algorithm and correct implementation of a solution to the previous state information problem. The initial time-frame algorithm determines the number of time-frames required to excite the fault under test and the number of time-frames required to observe the excited fault. This step saves the test generator from doing unnecessary search in the input space. Test generation is done strictly in forward time. The algorithm saves good machine circuit state after test generation to aid in future test generation. Faulty machine state is set to unknown whenever test generation for a fault is begun. This solves the previous state information problem, which has often been ignored by existing test generators. >

State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.

The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method. >

This research was supported in part by the Semiconductor Research Corporation under contract SRC 95-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits.

Test generation using deterministic fault-oriented algorithms is highly complex and time consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. Genetic algorithms (GA's) have been effective in solving many search and optimization problems. Since test generation is a search process over a large vector space, it is an ideal candidate for GA's. In this work, we describe a GA framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS'89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools. >

The authors provide a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. The path is considered to be sensitizable only if the corresponding stuck type fault is found detectable by a sequential circuit test generator. A depth-first analysis of circuit topology that determines all paths between primary inputs, primary outputs and flip-flops employs a partial path hierarchy. All paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that: (1) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer, and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20%. >

Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

Symbolic and genetic techniques are combined in a new approach to sequential circuit test generation that uses circuit decomposition, rather than the algorithmic decomposition used in previous hybrid test generators. Symbolic techniques are used to generate test sequences for the control logic, and genetic algorithms are used to generate sequences for the datapath. The combined sequences provide higher fault coverages than those generated by existing deterministic and GA-based test generators, and execution times are significantly lower in many cases.

We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more efficient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem. We develop heuristics to solve this optimization problem, then apply these heuristics as new test generation procedures. An empirical study comparing our heuristics to existing methods demonstrates the superiority of our approach, since our approach decreases the number of input vectors required for the test, translating into a reduction in the time and money required for testing sequential circuits.

The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

Automatic test pattern generation yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Scan techniques were used to break down the sequential ATPG problem to combinational test generation. As the overhead necessary for scan design can not be spent for all circuits, sequential test generation techniques gained importance. In this paper the FOGBUSTER (FOrward propaGation Backward jUstification Sequential Test genERation) algorithm is described and experimental results for the ISCAS '89 benchmark circuits are shown. FOGBUSTER is a complete algorithm which makes use of a forward propagation technique which is more efficient in general than the backward propagation technique used in the well known BACK-algorithm.

Automatic test pattern generation yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Scan techniques were used to break down the sequential ATPG problem to combinational test generation. As the overhead necessary for scan design can not be spent for all circuits, sequential test generation techniques gained importance. In this paper the FOGBUSTER (FOrward propaGation Backward jUstification Sequential Test genERation) algorithm is described and experimental results for the ISCAS '89 benchmark circuits are shown. FOGBUSTER is a complete algorithm which makes use of a forward propagation technique which is more efficient in general than the backward propagation technique used in the well known BACK-algorithm.

Search based algorithms for test sequence generation in functional testing