Si photonics technology for future optical interconnection

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

• We highlighted Silicon Photonics Technology Platform and its scalability to increased data rates, higher interconnect densities and low system level power dissipation. • Silicon photonics has been in production since 2009 and has shipped > 500K+ chipsets for use in High Performance Computing and Datacenters. • We made the trade-off between hybrid and monolithic integration of photonics and electronics. Hybrid Silicon Photonics allows cost effective integration of photonics with advanced electronic nodes. • By integrating 3rd Party IP in the electronic IC, hybrid integration enables a first level of ASIC integration with Photonics. • A next level of ASIC integration is enabled by a “Silicon Photonics Interposer” where photonic capabilities are combined with hybrid integration with electronics and TSV technology.

We have proposed and demonstrated a method for the fabrication of a SOI platform with custom-design device layer thickness ( 1 μm, operating at λ ~ 1550 nm. The input/output waveguides can be pigtailed with standard single-mode fiber with lensed tip ensuring modal overlap of >70% (coupling loss <1.5 dB). Such a multi-input multi-output SOI platform will facilitate for CMOS silicon photonics based on-chip applications with an additional usage freedom of device layer thickness. Moreover, it can be potentially used to design SOI based stand-alone devices which can be useful at transmitters/repeaters for short-haul/long-haul optical communication.

Silicon photonics (SiPh) are considered a promising technology for increasing interconnect speed and capacity while decreasing power consumption. Mode division multiplexing (MDM) enables signals to be transmitted in different orthogonal modes in a single waveguide core. Wideband MDM components simultaneously supporting wavelength division multiplexing (WDM) and orthogonal frequency-division multiplexing (OFDM) can significantly increase the transmission capacity for optical interconnects. In this work, we propose, fabricate and demonstrate a wideband and channel switchable MDM optical power divider on an SOI platform, supporting single, dual and triple modes. The switchable MDM power divider consists of two parts. The first part is a cascaded Mach–Zehnder interferometer (MZI) for switching the data from their original TE0, TE1 and TE2 modes to different modes among themselves. After the target modes are identified, mode up-conversion and Y-branch are utilized in the second part for the MDM power division. Here, 48 WDM wavelength channels carrying OFDM data are successfully switched and power divided. An aggregated capacity of 7.682 Tbit/s is achieved, satisfying the pre-forward error correction (pre-FEC) threshold (bit-error-rate, BER = 3.8 × 10−3). Although up to three MDM modes are presented in the proof-of-concept demonstration here, the proposed scheme can be scaled to higher order modes operation.

Bandwidth requirements continue to drive the need for low-power, high speed interconnects. Harnessing the mature CMOS technology for high volume manufacturing, Silicon Photonics is a top candidate for providing a viable solution for high bandwidth, low cost, low power, and high packing density, optical interconnects. The major drawback of silicon, however, is that it is an indirect bandgap material, and thus cannot produce coherent light. Consequently, different integration schemes of III/V materials on silicon are being explored. An integrated CMOS tunable laser is demonstrated as part of a composite-CMOS integration platform that enables high bandwidth optical interconnects. The integration platform embeds III-V into silicon chips using a metal bonding technique that provides low thermal resistance and avoids lattice mismatch problems. The performance of the laser including side mode suppression ratio, relative intensity noise, and linewidth is summarized.

We demonstrate a genetic algorithm based system that can optimize optical interconnects using silicon photonic multi-core fibre coupled transceiver. The GA selects 48 parameters to deliver a minimum 6.9×10−16 BER on channels with diverse losses.

In this paper, we demonstrated several AWG-based silicon photonics devices fabricated with deep UV lithography on SOI platform, including cascaded AWG, AWG-based receiver with fiber-to-waveguide converters, AWG-based OADM and folded AWG with ring-reflectors. In a thin top silicon layer, the silicon nanowire AWG has a performance of relative high crosstalk. In order to reduce the crosstalk, we designed and fabricated a 4-channel cascaded AWG. Compared to the normal single silicon photonics arrayed waveguide grating with a crosstalk of ~ -12.5 dB, the crosstalk of more than 20 dB has been dramatically improved in this cascaded AWG. The AWG-based OADM device is composed of two 1&times;8 AWGs, MZI thermo-optic switch array and crossing array, by which 8 signals can be loaded or uploaded. The channel spacing is around 3.2 nm at the wavelength of 1550nm and the crosstalk is less than -20 dB. The dynamic extinction is around 15 dB by thermal effect and the power consumption for a single channel is less than 12.3 mW. The 8-channel receiver was designed and fabricated on a SOI wafer with 1&micro;m-thick top silicon layer, which was composed of 5&times;8 AWG and 8 Ge-based butt-coupled photodetector array. The AWG device was designed on a thick SOI wafer for a good crosstalk performance. However, The silicon waveguide with a height of 1&micro;m has a coupling issue with a cleaved standard optical fiber. In order to reduce the coupling loss with the cleaved fiber, a new cantilevered fiber-to-waveguide converter was designed to integrate at the output/input waveguide of this receiver. The measured coupling loss of this converter is around 2.4dB/facet by using a cleaved single mode fiber. The 3dB-bandwidth of this butt-coupled photodetector is more than 30 GHz at a reverse bias of -1V. The transmission capability of this receiver is more than 400Gbps. Compared to other silicon photonics devices, the AWG size is not small. A 1&times;4 folded silicon photonics AWG was designed and fabricated on a SOI wafer with 340nm-thick top silicon layer. This folded AWG was integrated with ring-mirrors at the end of arrayed waveguides. The optical signals are launched into the input waveguide and coupled into the arrayed waveguides through the input slab waveguides. At the end of arrayed waveguides, the signals are reflected by the ring-mirrors. The reflected signals go back to the arrayed waveguides and the input slab waveguide in sequence, and then they are separated into the four output waveguides. The measured transmission loss of this folded AWG is about 3.5 dB and the crosstalk is around 20 dB. The measured channel spacing is 6.7 nm. This size of the demonstrated arrayed waveguide grating is only half of the normal arrayed waveguide grating. Acknowledgment： This work was supported by the National Natural Science Foundation of China (No. 61674072, No. 61565011 and No. 51304097).

We report new developments on hybrid integration that attaches CMOS driver circuits to silicon photonic (SiPhotonic) devices built in Silicon on Insulator (SOI) technology. This low-parasitic hybrid integration approach enables energy efficient links based on aggressive silicon photonic devices and low power, high speed circuits. The silicon photonic components are fabricated in the 130 nm Cu node of Freescale's SOI-CMOS technology while the CMOS driver circuits are fabricated in 40 nm TSMC ELK technology. The two types of chips are using 20 μm diameter solder bumps. We further present progress on scaling these solder bumps to 10 micron diameter and below as well as developing a wafer scale microsolder process module. Finally, we report progress integrating hybrids that include SOI chips with a partially removed backside. Under full SOI handler removal this bonding geometry is akin to the extreme limit of wafer thinning used in today's vertical chip stacking (3D) approaches.

The rapid scaling of microprocessor technologies has led to unprecedented advancements in processing speed and transistor density. However, as device dimensions shrink below the nanometre scale, traditional electrical on-chip interconnects face critical limitations including increased signal delay, power consumption, and reduced bandwidth. These challenges have emerged as major bottlenecks in the performance and energy efficiency of modern microprocessors, especially in multi-core and many-core architectures. To overcome these limitations, optical interconnects have gained significant attention as a high-performance alternative for on-chip and chip-to-chip communication. Optical interconnects offer key advantages such as higher data rates, lower latency, reduced power dissipation, and immunity to electromagnetic interference. The integration of optical components like waveguides, modulators, photodetectors, and silicon photonics within the chip architecture has the potential to revolutionize interconnect design by addressing the shortcomings of conventional electrical wiring. This paper explores the evolution of on-chip interconnects, comparing the performance, scalability, and integration challenges of electrical and optical solutions in scaled microprocessors. It also discusses emerging hybrid interconnect architectures that combine the strengths of both technologies. A comparison is made between electrical and optical interconnects for different design criteria, based on projections about the future of optical devices. Around a tenth of the length of the chip's edge is the crucial dimension beyond which optical connectivity becomes preferable to electrical interconnect at the 22 nm technological node.

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.

Silicon photonics VOAs (variable optical attenuators) have been manufactured for the past several years in quantities of 100,000s per year. Can the lessons of high-volume VOA production apply to 100Gb/s silicon photonics transceivers as they scale beyond 100k units per year?

Carbon Nanotubes (CNTs), Graphene Nanoribbons (GNRs), and Optical Interconnects and carbon nanotubes present promising options for replacing the existing Cu-based global/semiglobal and local wires. In this chapter, the performance of these novel interconnects is quantified and compared with Cu/low-κ wires for future high-performance integrated circuits. For a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. GNRs outperforms Cu wire below the width of 7nm. For semiglobal and global wires, both optical and CNT options are compared with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density.

In this paper, the bandwidth density of misaligned free space optical interconnects (FSOIs) system with and without coding under a fixed bit error rate is considered. In particular, we study the effect of using error correction codes of various codeword lengths on the bandwidth density and misalignment tolerance of the FSOIs system in the presence of higher order modes. Moreover, the paper demonstrates the use of the fill factor of the detector array as a design parameter to optimize the bandwidth density of the communication. The numerical results demonstrate that the bandwidth density improves significantly with coding and the improvement is highly dependent on the used codeword length and code rate. In addition, the results clearly show the optimum fill factor values that achieve the maximum bandwidth density and misalignment tolerance of the system.

The only way to make silicon photonics technology completely exploitable at industrial level for volume production is to solve the manufacturing bottlenecks that nowadays limit the applicability of the technology, in particular related to the multiple optical interconnection and the III-V chip integration. This paper will give a survey, based principally on the work made at Inphotec labs, on the problems and the challenges related to the optical interconnections to silicon photonic devices and their impact on process automation. It will give some update to what we are currently doing and developing in our labs utilizing a custom state of the art pigtailing-automated bench, robotics, including their present limitations.

We review the state of the art and our perspectives on silicon and hybrid silicon photonic devices for optical interconnects in datacenters. After a brief discussion of the key requirements for intra-datacenter optical interconnects, we propose a wavelength-division-multiplexing (WDM)-based optical interconnect for intra-datacenter applications. Following our proposed interconnects configuration, the bulk of the review emphasizes recent developments concerning on-chip hybrid silicon microlasers and WDM transmitters, and silicon photonic switch fabrics for intra-datacenters. For hybrid silicon microlasers andWDM transmitters, we outline the remaining challenges and key issues toward realizing low power consumption, direct modulation, and integration of multiwavelength microlaser arrays. For silicon photonic switch fabrics, we review various topologies and configurations of high-port-count N-by-N switch fabrics using Mach–Zehnder interferometers and microring resonators as switch elements, and discuss their prospects toward practical implementations with active reconfiguration. For the microring-based switch fabrics, we review recent developments of active stabilization schemes at the subsystem level. Last, we outline several large challenges and problems for silicon and hybrid silicon photonics to meet for intra-datacenter applications and propose potential solutions. © 2015 Chinese Laser Press.