Problems, challenges, and a critical survey on automated silicon photonics packaging and optical interconnection

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

The rapid scaling of microprocessor technologies has led to unprecedented advancements in processing speed and transistor density. However, as device dimensions shrink below the nanometre scale, traditional electrical on-chip interconnects face critical limitations including increased signal delay, power consumption, and reduced bandwidth. These challenges have emerged as major bottlenecks in the performance and energy efficiency of modern microprocessors, especially in multi-core and many-core architectures. To overcome these limitations, optical interconnects have gained significant attention as a high-performance alternative for on-chip and chip-to-chip communication. Optical interconnects offer key advantages such as higher data rates, lower latency, reduced power dissipation, and immunity to electromagnetic interference. The integration of optical components like waveguides, modulators, photodetectors, and silicon photonics within the chip architecture has the potential to revolutionize interconnect design by addressing the shortcomings of conventional electrical wiring. This paper explores the evolution of on-chip interconnects, comparing the performance, scalability, and integration challenges of electrical and optical solutions in scaled microprocessors. It also discusses emerging hybrid interconnect architectures that combine the strengths of both technologies. A comparison is made between electrical and optical interconnects for different design criteria, based on projections about the future of optical devices. Around a tenth of the length of the chip's edge is the crucial dimension beyond which optical connectivity becomes preferable to electrical interconnect at the 22 nm technological node.

Transparent conductive oxides (TCOs) have attracted significant research interests for integrated photonics and silicon photonics due to their dramatic change of optical permittivity, which can be dynamically controlled by the gate voltage. In addition, TCO materials can be easily integrated with silicon photonic devices by sputtering and regular lithography process, which demonstrates great potentials for large-scale integration. We report our recent research progress of hybrid silicon-TCO photonic devices using TCO gate/high-K insulator (HfO2)/Si waveguides, which achieves both outstanding energy efficiency and high modulation bandwidth. The strategy for future on-chip optical interconnect systems will also be discussed in this presentation.

We review the state of the art and our perspectives on silicon and hybrid silicon photonic devices for optical interconnects in datacenters. After a brief discussion of the key requirements for intra-datacenter optical interconnects, we propose a wavelength-division-multiplexing (WDM)-based optical interconnect for intra-datacenter applications. Following our proposed interconnects configuration, the bulk of the review emphasizes recent developments concerning on-chip hybrid silicon microlasers and WDM transmitters, and silicon photonic switch fabrics for intra-datacenters. For hybrid silicon microlasers andWDM transmitters, we outline the remaining challenges and key issues toward realizing low power consumption, direct modulation, and integration of multiwavelength microlaser arrays. For silicon photonic switch fabrics, we review various topologies and configurations of high-port-count N-by-N switch fabrics using Mach–Zehnder interferometers and microring resonators as switch elements, and discuss their prospects toward practical implementations with active reconfiguration. For the microring-based switch fabrics, we review recent developments of active stabilization schemes at the subsystem level. Last, we outline several large challenges and problems for silicon and hybrid silicon photonics to meet for intra-datacenter applications and propose potential solutions. © 2015 Chinese Laser Press.

Silicon photonics has drawn increasing attention in the past few decades and is a promising key technology for future daily applications due to its various merits including ultra-low cost, high integration density owing to the high refractive index of silicon, and compatibility with current semiconductor fabrication process. Optical interconnects is an important issue in silicon photonic integrated circuits for transmitting light, and fiber-to-chip optical interconnects is vital in application scenarios such as data centers and optical transmission systems. There are mainly two categories of fiber-to-chip optical coupling: off-plane coupling and in-plane coupling. Grating couplers work under the former category, while edge couplers function as in-plane coupling. In this paper, we mainly focus on edge couplers in silicon photonic integrated circuits. We deliver an introduction to the research background, operation mechanisms, and design principles of silicon photonic edge couplers. The state-of-the-art of edge couplers is reviewed according to the different structural configurations of the device, while identifying the performance, fabrication feasibility, and applications. In addition, a brief comparison between edge couplers and grating couplers is conducted. Packaging issues are also discussed, and several prospective techniques for further improvements of edge couplers are proposed.

Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

Silicon photonics has become the key enabling technology in many sensor applications including light detection and ranging (LiDAR) systems because of its high integration, chip-scale footprint and CMOS-compatible process. Thanks to these advantages, optical phased array (OPA) based on silicon photonics has emerged as a solid-state LiDAR solution to replace mechanical LiDAR counterpart. In such a system, optical loss from each component of the OPA devices should be minimized, while the radiation efficiency from the radiators of the OPA devices should be maximized for extending the power budget of the LiDAR system. These components can improve their performances through the recently emerged inverse design method. In this study, we designed a novel grating structure which is one of the components of OPA and allows wide-band and high coupling efficiency of light using inverse design approach with the particle-swarm-optimization method. Considering Silicon-On-Insulator (SOI) platform with 220 nm thickness, the configuration of the grating structure is determined by the finite number of particles so that the height and width of the corrugations are optimized based on the objective of boosting the out-of-plane radiated power amount. Highly efficient and vertical emission was obtained using finite-difference-time-domain calculation in telecommunication window centered at around 1550 nm. Including additional constraints in the inverse design will allow the realization of multitude spatial field profiles of the radiated light that may have an important contribution for OPA, sensing, imaging, lasers and optical interconnection.

Bandwidth requirements continue to drive the need for low-power, high speed interconnects. Harnessing the mature CMOS technology for high volume manufacturing, Silicon Photonics is a top candidate for providing a viable solution for high bandwidth, low cost, low power, and high packing density, optical interconnects. The major drawback of silicon, however, is that it is an indirect bandgap material, and thus cannot produce coherent light. Consequently, different integration schemes of III/V materials on silicon are being explored. An integrated CMOS tunable laser is demonstrated as part of a composite-CMOS integration platform that enables high bandwidth optical interconnects. The integration platform embeds III-V into silicon chips using a metal bonding technique that provides low thermal resistance and avoids lattice mismatch problems. The performance of the laser including side mode suppression ratio, relative intensity noise, and linewidth is summarized.

Polymer materials offer a number of interesting features for the fabrication of optical waveguides when compared with other materials such as silica glass. Organic polymers have attracted a lot of attention due to their ease of fabrication and structural flexibility. These are important factors with regard to their use as packaging and optical interconnects. In addition, the thermo-optic (TO) coefficient of polymers is an order of magnitude larger than that of silica glass and some non-aromatic polymers have very low birefringence. These are desirable characteristics in terms of their application to such optical integrated devices as TO switches. Polymeric waveguide applications are therefore divided into two categories. The first comprises optical packaging and interconnects and the second, optical integrated devices. Nevertheless, polymeric materials have certain disadvantages. An optical waveguide must retain its optical and physical properties under a variety of environmental conditions including high temperature and high humidity. However, polymer materials do not have sufficient reliability and thermal stability except for polyimide and the like. To solve these problems, we have worked to develop new materials, processes and packaging.

The progressive blooming of silicon photonics technology (SiP) over the last decade has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. A key enabler is the resonant structures that can participate in both modulation and demultiplexing of a high throughput wavelength division multiplexed (WDM) photonic link. The optical and electro-optical properties of such devices are subject to various design considerations, operation conditions, and optimization procedures. We present recent technological advances in photonic links based on resonant structures and highlight the key challenges that must be overcome at a large scale. Furthermore, we discuss how the design space of these resonant devices, down to the geometrical parameters and fabrication errors, can affect the performance and reliability of a photonic link.

We discuss recent progress and challenges in realizing Bragg-grating devices on the submicron silicon-on-insulator platform for next-generation optical communications applications, such as on-chip optical interconnects and signal processing. In particular, we focus on grating-assisted, wavelength-selective couplers, known as contra-directional couplers (contra-DCs). In contrast to conventional two-port Bragg gratings operating in the reection mode, contra-DCs are four-port devices with very weak backreections and, therefore, can be easily integrated with other photonic components on a chip. In order to provide a reliable on-chip wavelength-division multiplexing (WDM) solution for high-speed optical interconnects, we have developed high-performance add-drop filters and, furthermore, wavelength multiplexers/demultiplexers with combined advantages of at-top responses, low insertion loss (< 1 dB), and low crosstalk (< -23 dB). These WDM devices are ultra-compact and highly tolerant to temperature uctuations (up to ±50 °C), showing great potential for large-scale integration and low-power consumption. We further discuss a novel four-port Bragg photonic resonator for high-speed, low-power optical switching. Using a coupler-chirped design with uniform Bragg gratings, we have recently achieved an on-chip, continuously tunable photonic delay line with low insertion loss. These system-orientated devices indicate great potential for large-scale integration of Bragg-grating-defined functions using CMOS-compatible silicon photonics technology.

Silicon photonics has developed into a mainstream technology driven by advances in optical communications. The current generation has led to a proliferation of integrated photonic devices from thousands to millions-mainly in the form of communication transceivers for data centers. Products in many exciting applications, such as sensing and computing, are around the corner. What will it take to increase the proliferation of silicon photonics from millions to billions of units shipped? What will the next generation of silicon photonics look like? What are the common threads in the integration and fabrication bottlenecks that silicon photonic applications face, and which emerging technologies can solve them? This perspective article is an attempt to answer such questions. We chart the generational trends in silicon photonics technology, drawing parallels from the generational definitions of CMOS technology. We identify the crucial challenges that must be solved to make giant strides in CMOS-foundry-compatible devices, circuits, integration, and packaging. We identify challenges critical to the next generation of systems and applications—in communication, signal processing, and sensing. By identifying and summarizing such challenges and opportunities, we aim to stimulate further research on devices, circuits, and systems for the silicon photonics ecosystem.

Surface gratings are key devices on photonic chips to enable a free-space light coupling or chip interfacing with optical fibers. These elements can be employed in a variety of applications, ranging from optical interconnects and sensing, to light detection and ranging (LIDARs) and free-space communications. For LIDARs and free-space communications, dualpolarization gratings are important in modern optical phased arrays. However, surface gratings in silicon photonics are intrinsically polarization-sensitive due to the strong geometrical birefringence of the waveguides. In this work, we present a design of polarization-insensitive photonic nano-antennas in the silicon-on-insulator (SOI) platform. The proposed antennas have a L-shaped radiating profile with sub-wavelength metamaterials to simultaneously provide polarization independence and high radiation efficiency. The optical antennas are designed on a 300 nm thick SOI with a 3 μm thick buried oxide layer. The antenna has a compact footprint of 6.5 μm x 3.18 μm and critical dimensions larger than 50 nm, which are feasible for public silicon-foundry processing and fabrication. At the nominal wavelength of 1.55 μm, the antennas have a radiation efficiency of 50% and 21% for the TE and TM polarized light, with emission angles of -17° and -21°, respectively. Polarization-independent nano-antennas in mature SOI platform offer great potential for multi-element photonic circuits required by LIDARs and free-space communications.

High-performance Ge photodetectors on silicon photonics platform for optical interconnect

In this study, thermal design and thermal management for a low-cost photonic integrated circuits (PIC) platform is proposed and analyzed. The involved PIC platform is targeted for various applications including optical communications, optical interconnects, signal processing and sensing. The module considered in this study consists of a rigid PCB made of FR4 material and a silicon photonics ICs platform on which a laser diode chip, a driver chip, and a trans-impedance amplifier (TIA) chip are jointed using solder balls. A kovar case is chosen for the module. For the thermal design and thermal management, two objectives are involved in this study. The first one is to reduce the thermal resistance from junction to ambient and the other one is to reduce the thermal cross talk between the driver/TIA chips and laser source chip. The following accomplishments are achieved in this study. The overall junction to ambient thermal resistance is reduced to a certain level and meets the design target. The thermal cross effect between the driver/TIA chips and the laser source chip is reduced by cutting a slot in the silicon photonic platform and implementing separated heat spreaders for these chips.