Side channel attacks on STTRAM and low-overhead countermeasures

Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.

In this paper, we propose a Side Channel Attack (SCA) model on Spin-Torque Transfer RAM (STTRAM) where an adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. Simulation results indicate that by monitoring write current, 50% of keys could be extracted using 2000 traces. Further improvement of attacks on write operation is also proposed. The read current is found to be more susceptible to leak the key. It reveals first byte in only 40 traces and leaks the entire key in as low as 400 traces. The results are then compared with Static RAM (SRAM) based cache. The attack model has been experimentally validated on read operation of commercial MRAM chip (STTRAM variant). Experimental results indicate that the attack can reveal correct key in 15 traces compared to 40 in simulation due to less algorithmic noise. To the best of our knowledge, this is the first comprehensive SCA study for STTRAM based cache for cryptographic application.

Modern high performance Chip Multiprocessor (CMP) systems rely on large on-chip cache hierarchy. As technology scales down, the leakage power of present SRAM based cache gradually dominates the on-chip power consumption, which can severely jeopardize system performance. The emerging nonvolatile Spin Transfer Torque RAM (STT-RAM) is a promising candidate for large on-chip cache because of the ultra low leakage power. However, the write operations on STT-RAM suffer from considerably higher energy as well as longer latency compared with SRAM which will make STT-RAM in trouble for write-intensive workloads. In this paper, we propose to integrate SRAM with STT-RAM to construct a novel hybrid cache architecture for CMPs. We also propose dedicated microarchitectural mechanisms to make the hybrid cache robust to workloads with different write patterns. Extensive simulation results demonstrate that the proposed hybrid scheme is adaptive to variations of workloads. Overall power consumption is reduced by 37.1% and performance is improved by 23.6% on average compared with SRAM based static NUCA under the same area configuration.

Spin Torque Transfer RAM (STT-RAM), a assuring possible choice of Static RAM for diminishing leakage power utilization. STT-RAM has the resistance of the MTJ (Magnetic Tunnel Junction) that changes based on stored data. By using differential sensing with reconfigurable cache cell, the STT-RAM performance can be improved. This scheme largely reduces the read disturbance error and average power dissipation with small reading current. Furthermore reducing the power dissipation of STT-RAM, we introduce one new approach as Adiabatic (Energy recovery) Technique. Adiabatic Technique main motive is to reduce the average power dissipation with no performance degradation. The Adiabatic logic and memory are attractive solution for low power application.

There is growing interest in emerging non-volatile memory technologies such as Phase-Change Memory, Memristors, and Spin-Transfer Torque RAM (STT-RAM). STT-RAM, in particular, is experiencing rapid development that can be difficult for memory systems researchers to take advantage of. What is needed are techniques that enable designers to explore the potential of recent STT-RAM designs and adjust the performance without needing a detailed understanding of the physics. In this paper, we present the STeTSiMS STT-RAM Simulation and Modeling System to assist memory systems researchers. After providing background on the operation of STT-RAM magnetic tunnel junctions (MTJs), we demonstrate how to fit three different published MTJ models to our model and normalize their characteristics with respect to common metrics. The high-speed switching behavior of the designs is evaluated using macromagnetic simulations. We have also added a first-order model for STT-RAM memory arrays to the CACTI memory modeling tool, which we then use to evaluate the performance, energy consumption, and area for: (i) a high-performance cache, (ii) a high-capacity cache, and (iii) a high-density memory.

Research efforts to develop a novel memory technology that combines the desired traits of non-volatility, high endurance, high speed and low power have resulted in the emergence of Spin Torque Transfer-RAM (STTRAM) as a promising next generation universal memory. However, the prospect of developing a non-volatile FPGA framework with STTRAM exploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework; identify the key design challenges; and propose optimization techniques at circuit, architecture and application mapping levels. Simulation results show that a STTRAM based optimized FPGA framework achieves an average improvement of 48.38% in area, 22.28% in delay and 16.1% in dynamic power for ISCAS benchmark circuits over a conventional CMOS based FPGA design.

Artificial intelligence Internet of Things (AIoT) systems need more processing capability and low energy consumption on the terminals. Increasing the cache capacity at the architecture level can effectively reduce the cache missing rate and the number of off-chip memory access, which improves the performance of processors. Because of the limitation of the storage density and high leakage currents, improving SRAM cache capacity will lead to big chip area and high power consumption of processors. Emerging non-volatile memory (NVM), such as spin-transfer torque RAM (STT-RAM), has some characters such as bit width read/write and short read/write latency which are attractive options for replacing or augmenting SRAM. However, the asymmetric read/write latency of NVM brings some new challenges in designing caches. In this paper, we introduce a method to bring STT-RAM into the cache system of AIoT processors. Experimental results show that if we replace SRAM L2 cache with the same sized STT-RAM L2 cache, the out-of-order processor performance is improved up to 10 percent. We first find that for the STT-RAM cache, although the better-performing stream-based data prefetch configuration can improve the processor performance, the amount of prefetching data also increases obviously, which has negative effect on the processor performance because of the cache congestion caused by STT-RAM's long write latency. This paper presents a novel stream-based prefetch method ANCP (Adaptive Non-volatile Cache Prefetch) to reduce the amount of prefetch-write on STT-RAM. Compared with the best-performing stream-based data prefetch configuration, ANCP reduces the prefetching issued by 11 percent on average, which obtains additional up to 8 percent performance improvement of the AIoT processor.

Energy efficiency has become one of the primary considerations in the designs of cyber-physical systems (CPS). However, CPS with static RAM (SRAM)-based processors suffers from the high leakage power issue of SRAM, thus limiting the energy efficiency of CPS. Recently, Spin-Transfer Torque RAM (STT-RAM) has emerged and been widely regarded as a great alternative as the on-chip memory within processors, owing to STT-RAM's high density and near-zero leakage power characteristics. In addition, recent advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to further enhance the memory density. Nevertheless, the write disturbance issue greatly limits the energy efficiency of MLC STT-RAM. Even though studies have been proposed to alleviate this issue, most of the previous disturbance reduction strategies could induce additional management overhead by utilizing counters or cause frequent swap operations when the write disturbance happens. Such observations motivate us to propose a simple and effective solution to unify the direct and split mapping cache designs for improving the energy efficiency of MLC STT-RAM. The proposed design is evaluated through a series of experiments on an emulator with encouraging results.

Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel approach for redesigning STT-RAM memory cells to reduce the high dynamic energy and slow write latencies. We lower the retention time by reducing the planar area of the cell, thereby reducing the write current, which we then use with CACTI to design caches and memories. We simulate quad-core processor designs using a combination of SRAM- and STT-RAM-based caches. Since ultra-low retention STT-RAM may lose data, we also provide a preliminary evaluation for a simple, DRAM-style refresh policy. We found that a pure STT-RAM cache hierarchy provides the best energy efficiency, though a hybrid design of SRAM-based L1 caches with reduced-retention STT-RAM L2 and L3 caches eliminates performance loss while still reducing the energy-delay product by more than 70%.

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.

Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for Universal memory. However, there are two challenges to using STT-RAM in memory system design: (1) the intrinsic variation in the storage element, the Magnetic Tunnel Junction (MTJ), and (2) the high write energy. In this paper, we present a physically based thermal noise model for simulating the statistical variations of MTJs. We have implemented it in HSPICE and validated it against analytical results. We demonstrate its use in setting the write pulse width for a given write error rate. We then propose two write-energy reduction techniques. At the device level, we propose the use of a low-M S ferromagnetic material that can reduce the write energy without sacrificing retention time. At the architecture level, we show that Invert Coding provides a 7% average reduction in the total write energy for the SPEC CPU2006 benchmark suite without any performance overhead.

TAMPER presents a novel write-energy-aware driver circuit to decrease Write Error Rate (WER). Complementary metal-oxide-semiconductor, abbreviated as CMOS are vulnerable to serious shortage in designing parameters such as leakage power, scalability, and vulnerability to soft errors for designing a high dencity circuits. Spin Transfer Torque RAM (STT-RAM) is known as the most promising candidate for replacement the current memory technologies according to non-volatility characteristic. write errors occur in this technology primarily because of the process variation phenomenon. Write errors associated with different current densities is one of the major drawbacks of STT-RAM, also seen elsewhere in similar devices and a possible solution to such is presented and discussed in TAMPER. A thermal assistant write driver circuit is proposed, which has the ability to eliminate the process variation on write operation. By using this thermal assistance the asymmetric behavior of Magnetic Tunneling Junction (MTJ) over writing two states "0" and "1" decrease, which leads to reduce the time and energy needed for the writing operation. Experimental simulations have been done and compared with existing methodologies to validate the design. Power, performance, and WER enhancement by optimization in physical characteristics of transistors is achieved with on average 38.68% improvement of write time latency along with a 1.41% decrease in area.

Currently, commercial semiconductor-based memories face the problem of static energy consumption caused by leakage currents. Magnetoelectric random access memory (MeRAM), as a type of nonvolatile memory, provides a solution to this problem and can be used to replace the entire memory hierarchy as a universal memory. In contrast to spin transfer torque RAM (STT-RAM), MeRAM uses voltage controlled magnetic anisotropy (VCMA) effect to manipulate the switching of magnetic tunnel junctions (MTJs). MeRAM or VCMA-MTJ technology is more energy efficient and less likely to break down than STT-RAM. However, VCMA-MTJ suffers from serious write problems caused by variations in the VCMA coefficient, the external in-plane magnetic field, and the CMOS process. In this paper, a compact and SPICE-compatible VCMA-MTJ model is proposed. Then, a self-adaptive write circuit is proposed in which the write process is robust to variations in the VCMA coefficient and the external in-plane magnetic field. Finally, two practical methods are proposed to make our proposed self-adaptive write circuit also robust to 3$\sigma$ CMOS process variations, as demonstrated by Monte Carlo simulations. The proposed self-adaptive write circuit can assist in the design of next-generation high-speed, low-power MeRAM chips.

If spin-transfer torque RAM (SPRAM) technology is used as a true nonvolatile RAM, it will be able to provide normally “off” and instant “on” functions. This would drastically reduce the power consumption of information technology (IT) equipment and its infrastructure while preserving high performance, thus leading to a green IT infrastructure. This paper describes the design issues and solutions for creating a Gb-scale SPRAM; scaling in memory cell current (∝F, F: feature size) and the tunneling magnetoresistive (TMR) device’s write current (∝F2), the maximum voltage applicable to a TMR device (TMR ratio and resistance area product are considered); and the thermal stability of the TMR device (depending on the operation mode and density). Moreover, the cell and array configurations and an indispensable disruptive reading operation are shown for 4F2DDRx compatible operations. SPRAM can cover a system composed of a DRAM region. Finally, the potential of a multibit memory structure that covers the area of a not-and flash memory is discussed.