Signal Analysis of Software Defined Radio on Field Programmable Gate Array

This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency.

Multi-Party Computation (MPC) is a technique enabling data from several sources to be used in a secure computation revealing only the result while protecting the original data, facilitating shared utilization of data sets gathered by different entities. The presence of Field Programmable Gate Array (FPGA) hardware in datacenters can provide accelerated computing as well as low latency, high bandwidth communication that bolsters the performance of MPC and lowers the barrier to using MPC for many applications. In this work, we propose a Secret Sharing FPGA design based on the protocol described by Araki et al. We compare our hardware design to the original authors' software implementations of Secret Sharing and to work accelerating MPC protocols based on Garbled Circuits with FPGAs. Our conclusion is that Secret Sharing in the datacenter is competitive and when implemented on FPGA hardware was able to use at least 10× fewer computer resources than the original work using CPUs.

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flip-flops, and memory for the different configurations of the network (N = 10, 20 ….100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes.

Cyber is concerned with networks of systems in all their possible forms. Electronic warfare (EW) is focused on the many different uses of the electromagnetic spectrum (EMS). Given that many networks make use of the EMS (wireless networks), there is clearly large scope for collaboration between the cyber-warfare and EW communities. Unfortunately, such collaboration is complicated by the significant differences between these two realms. Software-defined radio (SDR) systems are based on interfaces between the EMS and computers and thus offer tremendous potential for encouraging cyber-EW collaboration. The concept of SDR is reviewed along with some hardware and software SDR systems. These are then used to propose a number of projects where SDR systems allow collaboration between the cyber and EW realms to achieve effects which neither realm could achieve alone.

Hardware-in-the-Loop (HWIL) simulation is becoming increasingly important for cost-effective testing of imaging infrared systems. DSTO is developing real-time scene generation and image processing capabilities within its HWIL simulation programs, based on the application of COTS desktop PCs equipped with Graphics Processing Unit (GPU) cards, and including limited use of Field Programmable Gate Arrays (FPGAs). GPUs and FPGAs are high-performance parallel computing machines but are fundamentally different types of hardware. To determine which hardware type should be used to implement a real-time solution of a given application, a methodology is required to expose the concurrency within the problem and to structure the problem in a way that can be mapped to the hardware types. In this paper we use parallel programming patterns to compare the architectures of recent generation GPUs and FPGAs. We demonstrate the decomposition of a parallel application and its implementation on GPU and FPGA hardware and present preliminary results.

Because of the recent slowdown in silicon technology and increasing power consumption of hardware, several dedicated architectures have been proposed in High Performance Computing (HPC) to exploit the limited number of transistors in a chip with low power consumption. Although Field-Programmable Gate Array (FPGA) is considered as one of the promising technologies to realize dedicated hardware, it is difficult for non-domain experts to program FPGAs due to the gap between thier applications and hardware-level programming models for FPGAs. In this paper, we propose a C/C++ based programming framework, C2SPD, to describe stream processing on FPGA. It uses SPGen, a dataflow High Level Synthesis (HSL) tool, as the FPGA backend. C2SPD can program FPGAs by adding directives to serial code, and the compiler translates it into optimized SPGen code. The range of application is limited in C2SPD due to its domain-specific approach. However it can generate efficient hardware on FPGAs when the programming model matches the target application. 2D-stencil computation is written in C2SPD to evaluate the performance of our C2SPD compiler implementation. 2 lines of the C2SPD directives are added into the serial C code to generate FPGA hardware. The Optimized FPGA hardware achieves 175.41 GFLOPS by using 256 stream cores, which is 220 times faster than a single stream core.

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

The demand for low-power devices has significantly increased across various applications, highlighting the crucial role of VLSI technology due to its unique capabilities. Traditional data acquisition systems often utilize embedded and ASIC devices, but these devices typically fail to meet the low-power requirements of modern applications. As an alternative, Field Programmable Gate Array (FPGA)-based solutions have emerged as effective candidates for data acquisition systems. This paper presents the implementation of a data acquisition system (DAQ) on a Basys 3 FPGA board utilizing both MicroBlaze and Zynq processors. Temperature sensors, ultrasonic sensors, and OLED peripherals are interfaced and executed on FPGA hardware. The Xilinx Vivado software serves as the design tool to integrate hardware components and processors, employing Verilog as the hardware description language. Performance evaluation confirms that FPGA devices effectively handle DAQ applications at a clock frequency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 0 0 ~ M H z}$</tex>.

Median filtering is an important approach in digital image processing for noise elimination. An improved median filtering algorithm (IMFA) is proposed which can be implemented with only 17 comparisons and 6 clocks delay for 3×3 median filtering mathematical model based on field programmable gate array (FPGA). The algorithm benefits from the parallel processing and pipelining structure of FPGA hardware. At first, the characteristics, basic operational principle and computing process of the IMFA are presented. And then the algorithm using modular technique and top-down design flow methodology with Verilog HDL are programed. At last, some simulation verifications for the algorithm by ModelSim and experimental verification on FPGA hardware platform are carried out. The IMFA can get a large number of data throughput and more quickly processing speed and less hardware resources than similar filtering algorithms.

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

For extended mission utility, it is desirable to be able to reprogram on -orbit payloads for new functions not originally envisioned. The basic concept of modifying payloads in orbit is already proven in that software patches and new coding algorithms can be uploaded to payloads years after launch. The goal of this paper is to discuss the option to extend this reprogrammability to payload hardware, using standards and architectures proven in software -defined radio technology. Next generation payloads using these standards can exploit the increasing versatility and density o f modern Field Programmable Gate Arrays and Digital Signal Processing chips to perform new missions that require onboard wideband, real time processing. I. Introduction HIS paper discusses the application of proven software standards and design methodology to enable next generation multifunction payloads. Even though the physics of specific front -end sensors, emitters and associated electronics in the payload must conform to the original mission, the trend is moving toward increasing generalization and digi tal processing onboard, along with more generalized digital control of the front ends . New missions can take advantage of this trend by relying on generalized hardware that is programmed to be mission specific and reprogrammed as missions change . As onbo ard processing bandwidths increase over time, to tens and hundreds of Megahertz, these missions will benefit from the ever -increasing performance of digital technology in field -programmable gate arrays (FPGAs) to achieve their original and future objective s, increasing the payloads’ effectiveness while reducin g size, weight, power and cost. This approach also benefits operationally responsive satellite missions by reducing the serial development cycle, as a result of reusing common hardware and applying pro ven software to the task of on -orbit reconfiguration. Reconfiguring and reprogramming the FPGA -based payload in the field is similar to sending a new software load to an onboard microprocessor. However, the standards for uploading new functionality to a hardware target are not in such a mature form as for software, which use operating systems and monitor programs that can accommodate new program uploads . This paper specifically suggests the use of modern software -defined radio (SDR) standards to be appl ied more widely, to enable management and upgrading of generalized hardware -based, wideband payload functions. Figure 1 shows the generalized block diagram of a reconfigurable payload.

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

Software defined radio (SDR) is a vast and emerging field that requires the design of various technologies such as antenna, RF, IF, and digital baseband subsystems. Among all these technologies, data converters that convert signals between analog and digital domains are highly crucial. On the other hand field programmable gate arrays (FPGAs) based platforms are being preferred for evaluating and implementing the digital communication concepts due to their programmability and reconfigurability. As a result they are well suited for the design of SDR technology. In this research work, we develop a platform where high-speed data converters are interfaced with high performance FPGAs. Interfaces are designed for analog-to-digital convertors (ADC) and digital-to-analog convertors (DAC) to communicate with FPGAs. For the interface design between ADC and FPGA, a double data rate and a low voltage differential signalling based serial output is adopted. And, for the interface design between DAC and other FPGA, parallel complementary metal oxide semiconductor outputs are used. To reconfigure the modes and parameters of the data convertors, serial peripheral interface data controllers have been designed. We have through simulations evaluated the performance of our designed interfaces between data convertors and FPGAs.

Software Defined Radios (SDRs) are wireless communication systems in which many of the radios' important functional elements, including filtering, frequency translation and modulation/demodulation, are implemented in software via Digital Signal Processing (DSP) techniques using embedded processors and Field Programmable Gate Arrays (FPGA) as described by Harris and Lowdermilk in 2010 [1]. SDRs differ from traditional radios that typically employ custom silicon to implement such functions. SDRs exhibit several advantages over traditional radios, including re-configurability and reduced development costs and time-to-market since they do not require custom silicon. SDRs also enjoy long life cycles, since they can readily be adapted to meet future needs. Cognitive Radios (CRs) are a special class of SDRs that employ adaptive DSP technologies to implement spectral management. This enables CRs to deliver improved effective bandwidth, quality of service, and enhanced security, which have become increasingly important in modern commercial and military wireless communications applications.

Simultaneous Localization and Mapping (SLAM) is a system used to achieve autonomous positioning and navigation. Feature detection is an important part of a SLAM system as fast and robust image matching is required for the task. A typical feature detection algorithm called Speeded-Up Robust Features (SURF) is used in a robot SLAM system with Moving Object Detection (MOD). This paper describes a modified feature detection algorithm based on Field Programmable Gate Array (FPGA) hardware. The paper focuses on implementing the software algorithm on a hardware platform. The advantage of the parallel and pipelining design of FPGA is fully applied to highly improve the performance and efficiency of the system. By using the FPGA hardware platform, the algorithm can also be implemented easily in an FPGA-based SLAM system afterward to finally use for System-On-Chip (SoC) applications.