Single tests for logical gates

In design systems for digital VLSI (very large integrated circuits), the BDD is used for VLSI verification, as well as for technologically independent optimization, performed as the first stage in the synthesis of logic circuits in various technological bases. BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. Having constructed BDD representation for systems of Boolean functions, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction or conjunction of other cofactors of this BDD level. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from library logic gates.

Card-based cryptography allows us to securely compute arbitrary functions using a deck of physical cards. Its performance is mainly measured by the number of used cards and shuffles, and there is a line of work that aims to reduce either of them. One seminal work is the card-based garbled circuit technique by Shinagawa and Nuida (Discret Appl Math 289:248–261, 2021, https://doi.org/10.1016/j.dam.2020.10.013), which allows the construction of a card-based protocol for any Boolean function with a single shuffle. Their construction requires 2n+24g cards for an n-input Boolean function that is represented by g logical gates. In this paper, we reduce the number of cards to 2n+8g for arbitrary functions while keeping it working with only one shuffle. In addition, we propose two types of extensions to support numerical encoding and multi-input gates. In the extended scheme, the free-ADD technique, obtained by generalizing the free-XOR technique by Manabe and Shinagawa (Deng J, Kolesnikov V, Schwarzmann AA (eds) CANS 2023, LNCS, vol 14342. Springer, Singapore, pp 232–248, 2023, https://doi.org/10.1007/978-981-99-7563-1-11), is available. The free-ADD technique allows our scheme to evaluate any n-input symmetric Boolean function using 2n2+6n+2 cards.

The concept of truth table is based on the content to analyze in teaching and learning logical reasoning and logic gate, which is a visual representation of possible combination of input and output information of Boolean prepositions in logical reasoning and Boolean functions in logic gate plotted into a table. It adopts Boolean algebra for problem solving as a method or science of reasoning, or ability to argue and convince. In the teaching and learning processes of logic, formal and informal reasoning tasks are used in a variety of ways, including using symbols and entirely in plain language without symbols where symbolic logics are commonly referred to as mathematical logic. This paper therefore considers the Use of Truth Table, Logical Reasoning and Logic Gate in Teaching and Learning Process It highlighted the benefits of using the truth table and compared logical reasoning and logic gate connectives and concluded that, there exist similarities, differences and peculiarities in the interactive features of the content of the truth table. The paper suggested that teachers should vividly state the similarities, differences and peculiarities in the interactive features of truth table in logical reasoning and logic gate while incorporating thought in teaching and learning process to avoid confusion.

Abstract. Background. Computer circuits enable almost every piece of electronics to function. An opportunity for their optimization was found in one of the ways to implement a circuit, which involves a decoder. Decoders are basic circuit components whose behavior makes it easy to implement multiple Boolean functions. Functions are just rules by which informational signals are being processed in the circuit. To implement a function Logic gatEs (LEs) are used. LEs group multiple input signals and process them using binary logic operators like AND or NOR. Purpose. Develop a computer program that, based on provided functions, will find a solution associated with approximately minimal number of logic gates. Relevance. Prevalence of circuits increases the value of small optimizations, since any improvement gets multiplied by millions of circuits produced. Optimization at the logic level is being explored, which will retain value regardless of the physical properties of the circuit. Additionally, the theory of optimizing LE usage for circuits built on decoders is examined, which will alleviate future research. Methods. Development of the theory arose from an understanding that input signals can be grouped using LEs consciously. This way, LE outputs can be used in more than one function, which results in reduction of total number of LEs. It becomes evident that the problem can be restated in terms of sets. Similarity to known NP-hard problems emerges, which prompts usage of existing solution approaches. Among them, the greedy algorithm is chosen for its simplicity in program implementation. The connection between the problem and digital circuitry is weakened by the introduction of special evaluation functions that work with sets. So, the problem is reduced to several mathematical rules, which then are used as the appropriate parts of the greedy algorithm. Development of knowledge necessary to create the target program is thus concluded. Results. The target program is successfully implemented and can be seen in full at https://github.com/Gleb-05/MakeFuncForDC. A test is conducted on 1000 sets of four pseudorandom eight-term functions. It is estimated that the implementations proposed by the program require on average 0.75 of the initial number of LEs. The average running time is estimated at 2 milliseconds. In contrast, brute-force search for the same problem is theorized to run for years. Conclusions. A working program that finds an almost optimal solution is successfully created and tested. Its performance makes it potentially useful in the industrial scale of circuit manufacturing. Since the program essentially offers workload management, its possible applications go beyond the domain of digital electronics. Additionally, the theory of optimizing the use of LEs is presented for the first time. It can be used as the basis for future research on the implementation of multiple Boolean functions using decoder.

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.

We consider problems of operability checking and state diagnosis of N functional elements realizing a given Boolean function f ∈ {x1 & ... &xn, x1 ∨ ... ∨ xn\(\overline {x_1 } \)} in their perfect states and including not more than k faulty elements by means of composition of one-output circuits from them and observation of values produced by these circuits on any value set of input variables. Arbitrary constant faults on outputs of functional elements are permitted. One has to minimize the number of circuits required for operability checking and determination the states of all elements. Lower bounds of the form ck(log2N − log2k) are obtained for the number of circuits.

Card-based cryptography allows us to securely compute arbitrary functions using a deck of physical cards. Its performance is mainly measured by the number of used cards and shuffles, and there is a line of work that aims to reduce either of them. One of the seminal work is by Shinagawa and Nuida (Discrete Applied Mathematics 2021) that shows any Boolean function can be constructed by shuffling only once based on the garbling scheme. Their construction requires $$2n + 24g$$ cards for an n-input Boolean function that is represented by g logical gates. In this paper, we reduce the number of cards to $$2n + 8g$$ for arbitrary functions while keeping it working with only one shuffle.

With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed [1]. While various manufacturing methodologies and camouflaged gates have been proposed, none fully address these threats, especially in combination. To address these concerns, we use post-manufacturing programmable camouflaged logic topology to simultaneously obscure the design IP from the manufacturer as well as combat reverse engineering. The basis of the design is a threshold-voltage-defined (TVD) logic gate topology that solely uses different threshold voltage implants to determine the logic gate function [2]. Every gate has an identical physical layout and is post-manufacturing programmed with different threshold voltages for different Boolean functions using intentional directed hot-carrier injection (HCI). Similar intentional HCI techniques have previously been used to enhance SRAM margins, boost PUF reliability, and build TRNGs [3][4]. The design is fully compatible with standard CMOS logic processes, requiring no special layers, structures, or process steps.

Quantum cellular automata (QCA) technology is a nanotechnology provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper discusses about the quantum cellular automata complex gate structure consist of 3, 4 and 5 input majority gates. Multi input complex gates can be constructed with the single QCA structure that can be configured in to Boolean functions and logic gates. We have also constructed product of sum and sum of product representation and other different Boolean functions. QCA circuits are simulated using QCAdesinger tool and waveforms are presented. We also validate the constructed structure by building combination al circuits like comparators etc. A single fixed QCA structure is useful for building module in QCA FPGA and ASIC applications.

The degree of a Boolean function is a basic primitive that has applications in coding theory and cryptography. This paper considers a problem of computing the degree of a perfect nonlinear Boolean function in a quantum system. The details are as follows: Given a promise that the function f is either linear or perfect nonlinear in $$F^{n}_{d}$$ , we propose a quantum algorithm 1 to distinguish which case it is with a high probability, where d is an even number. Furtherly, for computing the degree of a perfect nonlinear Boolean function f, we present a quantum Algorithm 2 to solve it by calling quantum Algorithm 1 when $$d=2$$ . The quantum query complexity of the proposed quantum Algorithm 2 is O(s), and the space complexity (the number of quantum logic gate) is $$O(2^{s})$$ , where $$s+1=\text {deg}(f)$$ . The analysis shows that the quantum Algorithm 2 proposed in this paper is more efficient than any classical algorithm for solving this problem.

Conventional processors often underutilize their computational resources because of the fixed functionality of logic gates; numerous logic gates should be embedded to support all necessary operations, even if many of them are rarely used. Reconfigurable logic gates (RLGs) offer a promising solution as they dynamically switch their logical functionality according to the demands of specific operations. Here, a novel RLG architecture based on the dual‐gate silicon nanomembrane (SiNM) field‐effect transistors (FETs) is proposed. By reconfiguring the electrostatic doping profiles of the SiNM channel, the dual‐gate SiNM FET can operate as three distinct electronic components; a forward‐biased diode, a backward‐biased diode, and a variable resistor. Furthermore, the three dual‐gate SiNM FETs are integrated to implement a single RLG, whose Boolean logic functions can be reconfigured between AND and OR operations. In addition, an array of three RLGs can be used to perform 32‐bit masking operations, thereby validating their effectiveness in digital data processing.

In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Stimuli-responsive multistep switching phenomena of a luminescent bimetallic Ru(II) complex are employed herein to fabricate multiple configurable logic devices. The complex exhibits "off-on" and "on-off" emission switching upon alternative treatment with visible and UV light. Additionally, remarkable augmentation of the rate as well as quantum yield of photoisomerization was achieved via the use of a chemical oxidant (Ce4+) as well as a reductant (metallic sodium). Upon exploiting the emission spectral response of the complex, several advanced Boolean logic functions, including IMPLICATION as well as 2-input 2-output and 3-input 2-output complex combinational logic gates, are successfully implemented. Additionally, by utilizing the vast efficacy of Python, a novel "logic_circuit" model is devised that is capable of making accurate decisions under the influence of various input combinations. This model transcends traditional Boolean logic gates, offering flexibility and intuition to design logical functions tailored to specific chemical contexts. By integrating principles of logic circuits with chemical processes, this innovative approach enables structure determination of the chemical states based on input conditions, thereby unlocking avenues for exploring intricate interactions and reactions beyond conventional Boolean logic paradigms.

The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10W will be reported in this paper.

Growth hormone (GH) replacement has been offered to GH-deficient (GHD) children for approximately 40 years whereas it has only been a licensed indication for the treatment of GHD adults since 1996. Nonetheless, the advent of GH replacement for adult GHD patients (Jorgensen et al., 1989; Salomon et al., 1989) has proved informative about the overall management of the GHD child and teenager; equally, the longstanding experience of the paediatric endocrinologist with GH replacement has provided some guidance about potential pitfalls in the diagnosis and management of the adult GHD patient. It is the knowledge exchange at this professional interface that forms the focus of this article.