Soft computing programmable control systems-on-chip: Trends and surface polynomial modeling

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

Being lossless, Reversible Image Watermarking (RIW) with Difference Expansion (DE) algorithm is crucial for content authentication, especially for high security medical and military images. In DE-RIW, the secret data bit can be embedded into the Least Significant Bit (LSB) of the difference between two neighboring pixels. Very few researchers have worked on High Level Synthesis (HLS) based implementation of its modified algorithm on Field Programmable Gate Array (FPGA) and Programmable System-On-Chip (P-SoC). Here, to get accelerated performance a modified DE-RIW algorithm is proposed along with its VLSI based hardware implementation both on Xilinx FPGA and P-SoC. In the proposed approach, scheduling is done considering resource constraint criteria. Implementation results through simulation up to burning the design on board needs fewer resources (adder, subtractor, multiplier, divider, register, multiplexer, and comparator) as compared with the similar existing architectures in the literature based on RIW.

In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the computational performance of the implementation schemes. The experimental results show that the proposed schemes all have high precision and computational efficiency for vehicle state and friction force estimation.

Since embedded systems have such a wide range of applications in today's time, there is a pressing need to meet the design requirements such as power consumption, cost, time to market, flexibility and robustness. Power consumption by embedded systems is a particularly critical issue. This paper is a starting point for understanding power aware design methodologies, and it reviews the various techniques of designing power efficient embedded systems using Programmable System on Chip (PSoC). PSoC is a true programmable embedded SoC (System on Chip) which integrates configurable analog and digital components, memory and a microcontroller on a single chip thus providing high level of flexibility and configurability.

In this paper four simple but very effective image enhancement technique is implemented in a digital configurable block on Programmable System on Chip (PSoC). This is done by converting a 2D gray image matrix to 1D vector and send it to PSoC5 LP Universal Asynchronous Receiver Transmitter (UART).The UART is communicating with a Verilog component which use Universal Digital Block Array (UDB) for implementing image enhancement algorithms. For implementing enhancement algorithm very simple Verilog components are developed by using Cypress PSoC Creator 2.2, It includes adder, subtracter, multiplier, 8 bit comparator, and multiplexer. Verilog components for constant values are also developed. Enhancement algorithms are implemented with the integration of arithmetic, logical and constant Verilog components.

Based on Xilinx's Virtex-II Pro series device XC2VP30 FPGA (Field Programmable Gate Array) chip, we have designed the system to implement remote high-precision time data acquisition, control and processing using TCP/IP communication protocol. This paper describes the design and implement of the FPGA-based hardware platform and software, and the design of ethernet human-computer interaction interface in detail. FPGA-based SOPC (system on programmable chip) technology is the core of the system. Making full use of the FPGA logic cells and related peripheral controller can implement a reconfigurable chip system on FPGA, which can conduct data transmission with a remote control interface.

Parametric equalization is often used to achieve a desired response from an audio transmitter, but is rarely applied to ultrasonic transducer systems. The ability of a broadband ultrasonic transmission and reception system to adapt its frequency and time domain response to changing acoustic conditions would be a distinct advantage in certain applications. Ultrasonic remote monitoring systems would benefit significantly from this ability, as signal levels could be minimized and consequentially the transmitter power consumption decreased. This work presents a real-time adaptive ultrasonic parametric equalizer using optimization driven Matlab code to control the coefficients of a switched capacitor filter network implemented in a Cypress PSOC (Programmable System On a Chip). In this work, adaptive parametric magnitude equalization of a through-transmission ultrasonic system using CUTs (Capacitive Ultrasonic Transducers) has been achieved in real time by tracking a desired SNR (signal to noise ratio) across the operational frequency spectrum. A Matlab general radial basis function (GRBF) artificial neural network (ANN) was developed to control the equalization filter coefficients based on the received frequency response data. The adaptive parametric equaliser adjusts the magnitude of the driving signal to maintain the desired SNR as closely as possible. The neural network was trained using PSO (Particle Swarm Optimization) back-propagation, based on a state space model of the system developed from frequency response data. The developed equalization circuitry, which is switched capacitor based and was fully implemented on the PSOC, is also described.

We describe in this book, new methods for building intelligent systems using type-2 fuzzy logic and soft computing techniques. Soft Computing (SC) consists of several computing paradigms, including type-1 fuzzy logic, neural networks, and genetic algorithms, which can be used to create powerful hybrid intelligent systems. In this book, we are extending the use of fuzzy logic to a higher order, which is called type-2 fuzzy logic. Combining type-2 fuzzy logic with traditional SC techniques, we can build powerful hybrid intelligent systems that can use the advantages that each technique offers. We consider in this book the use of type-2 fuzzy logic and traditional SC techniques to solve pattern recognition problems in real-world applications. We consider in particular the problems of face, fingerprint and voice recognition. We also consider the problem of recognizing a person by integrating the information given by the face, fingerprint and voice of the person. Other types of applications solved with type-2 fuzzy logic and SC techniques, include intelligent control, intelligent manufacturing, and adaptive noise cancellation.

With the development of the nuclear technology, the instrumentation and control (I&C) systems have evolved from the analog systems to the current state-of-the-art digital systems. It has been reported that China has recently developed the digital systems based on Field Programmable Gate Array (FPGA) in CAP1400 nuclear power plant. And the lack of methods in the verification and validation work of the FPGA systems has become an important issue. This thesis describes the basic principles of FPGA, and the development process of FPGA. And then, the thesis proposes an effective improved method—formal verification, describing three methods of formal verification in detail, namely theorem proof, model checking, and equivalence proof. Describing the FPGA verification methodology and pointing out the shortcomings of traditional simulation, comparing the formal verification and traditional simulation verification in terms of complexity, timing, and applications. We also discussed the importance of formal verification method in FPGA. We selected the temperature and power control chip based on FPGA as an example, using System Verilog Assertions (SVA) method of model checking, and verifying the SRAM controller module and the internal calculation module. Through the analysis of the results, this paper proved the feasibility of formal verification methods in the instrumentation and control system of nuclear power plants, and provided some references of verification work for other system chips in instrumentation and control of nuclear power plant in the future work. The thesis showed that verification engineers can use the formal verification method based on SVA to verify the robustness of the system quickly and accurately. This method improves the controllability and observability which are the main drawbacks of the traditional simulation verification. It also avoids several issues in the debug process of traditional simulation verification, improving the accuracy and completeness of the chip verification.

Infant health monitoring is crucial for early detection of potential health issues. Many existing solutions, while effective, are often costly and designed for clinical settings, making them less accessible for home use. Parents require an affordable, easy-to-use solution to monitor their infant’s vital signs, such as body temperature and pulse, in real time. The rapid development of wireless communication technologies and microcontroller systems like Programmable System-on-Chip (PSoC) provides a new opportunity to create effective, low-power, and cost-efficient health monitoring systems tailored for home use. This study focuses on developing a remote infant health monitoring system that integrates wireless data transmission to enable real-time monitoring by parents. The proposed system consists of three modules: On-Child-Device, Child-Device, and Parent-Device. The On-Child-Device, worn by the infant, measures vital signs using a thermistor and an infrared pulse sensor. The data is processed by a PSoC microcontroller and transmitted wirelessly to the Child-Device, which then forwards the information to the Parent-Device for display. The Parent-Device provides a user interface where parents can monitor real-time data, including alerts for abnormal readings. The system’s hardware is built using PSoC technology, offering flexibility in integrating sensors and communication protocols. Software development was carried out using the PSoC Designer environment, which allows for real-time data acquisition, error checking, and wireless communication management. Initial testing of the system demonstrated reliable performance in measuring and transmitting vital signs. The wireless communication between the modules showed minimal latency, with real-time data accurately displayed on the Parent-Device. The use of PSoC technology enabled efficient power consumption, allowing the system to operate continuously for extended periods without frequent battery replacements. The system's modular design also proved adaptable, allowing for potential integration of addition-al sensors in the future. Feedback from users highlighted the intuitive interface of the Parent-Device, making it accessible for non-technical users. However, challenges related to signal interference in certain environments were noted, suggesting the need for further optimization of the communication protocol. The developed remote infant health monitoring system offers a cost-effective, energy-efficient solution for home use. By utilizing PSoC technology, the system provides reliable real-time monitoring of vital signs, ensuring that parents can quickly respond to any health abnormalities. The wireless transmission and user-friendly interface make the system practical for everyday use, filling a significant gap in current infant health monitoring technologies. Future improvements will focus on enhancing the communication robustness and integrating additional health metrics to provide a more comprehensive monitoring solution. Keywords : Telemetric data, Parental device, Health monitoring, Temperature sensor, Pulse measurement, Programmable System on Chip

SOPC (System on Programmable Chip) is an on-chip programmable system based on large scale Field Programmable Arrays (FPGAs). This paper presented an implementation of an SOPC system with a custom hardware neural network using Altera FPGA chip-EP2C35F672C. The embedded Nios processor was used as the test bench. The test result showed that the SOPC Platform with hardware neural network is faster than the software implementation respectively and the accuracy of the design meets the requirement of system. The verified SOPC system can closely model real-world system, which will have wide applications in different areas such as pattern recognition, data mining and signal processing.

This paper discusses the design and implementation of a wireless sensor node using a Programmable System on Chip (PSoC). The main aim of this paper is to highlight the use and need of a low cost system for monitoring various parameters where human presence is prohibited. The system was implemented using a PSoC 3 device and transceivers CC2500 RF wireless module.

Proposed wireless sensor node is a highly flexible and programmable system on chip (PSoC) architecture along with integrated RF radio chip, which can be adapted to any IEEE 802.15.4 standard based protocol, working at the band of 2.4GHz.This can be accompanied by the RF antenna matched with the interface circuit for various kinds of sensors and peripherals to form a wireless sensor node.This can be very well used to form a wireless sensor network in different domains.This proposed methodology can be used for specific application for improving the WSN stability and performance.This article will mainly present the design of wireless sensor nodes based on PSoC and CyFi radio chip, including the application specific antenna and hardware design for the system on chip for the sensor node and the simple introduction of the application domain.The proposed nodes are used with a special antenna and application based protocol for communication.This design has a better power handling and performing capacity.Further, we have implemented this for the wireless sensor node as well.

Due to the growing variety and quantity of information available on the Web, there is urgent need for developing Web-based applications capable of adapting their services to the needs of the users. This is the main rationale behind the flourishing area of Web personalization that finds in soft computing (SC) techniques a valid tool to handle uncertainty in Web usage data and develop Web-based applications tailored to user preferences. The main reason for this success seems to be the synergy resulting from SC paradigms, such as fuzzy logic, neural networks, and genetic algorithms. Each of these computing paradigms provides complementary reasoning and searching methods that allow the use of domain knowledge and empirical data to solve complex problems. In this chapter, we emphasize the suitability of hybrid schemes combining different SC techniques for the development of effective Web personalization systems. In particular, we present a neuro-fuzzy approach for Web personalization that combines techniques from the fuzzy and the neural paradigms to derive knowledge from Web usage data and represent the knowledge in the comprehensible form of fuzzy rules. The derived knowledge is ultimately used to dynamically suggest interesting links to the user of a Web site.

One of the main challenges in Systems designs is the ability to integrate real time high fidelity models on suitable and feasible hardware platforms. Because of its inherited parallelism, FPGA (Field Programmable Gate Arrays) technology achieves sample rates which are typically faster than real time. This can be seen as the last line of defence against the increasing requirements given by high fidelity models. But as most of the FPGA applications are specialised and the FPGA toolsets do not support basic control systems blocks, designs are constructed and optimised manually. This leads to significant effort required in finding feasible hardware FPGA implementations. Therefore, the work in this paper describes how to automatically optimise the most time consuming process found in generic FPGA implementations: the optimisation of the pipelining process. This is constructed on a rigorous mathematical model and achieved using drag and drop floating point HDL (Hardware Description Language) control systems blocks, under System Generator, in Simulink.