Real time adaptive parametric equalization of Ultrasonic Transducers

Since embedded systems have such a wide range of applications in today's time, there is a pressing need to meet the design requirements such as power consumption, cost, time to market, flexibility and robustness. Power consumption by embedded systems is a particularly critical issue. This paper is a starting point for understanding power aware design methodologies, and it reviews the various techniques of designing power efficient embedded systems using Programmable System on Chip (PSoC). PSoC is a true programmable embedded SoC (System on Chip) which integrates configurable analog and digital components, memory and a microcontroller on a single chip thus providing high level of flexibility and configurability.

In this paper four simple but very effective image enhancement technique is implemented in a digital configurable block on Programmable System on Chip (PSoC). This is done by converting a 2D gray image matrix to 1D vector and send it to PSoC5 LP Universal Asynchronous Receiver Transmitter (UART).The UART is communicating with a Verilog component which use Universal Digital Block Array (UDB) for implementing image enhancement algorithms. For implementing enhancement algorithm very simple Verilog components are developed by using Cypress PSoC Creator 2.2, It includes adder, subtracter, multiplier, 8 bit comparator, and multiplexer. Verilog components for constant values are also developed. Enhancement algorithms are implemented with the integration of arithmetic, logical and constant Verilog components.

SOPC (System on Programmable Chip) is an on-chip programmable system based on large scale Field Programmable Arrays (FPGAs). This paper presented an implementation of an SOPC system with a custom hardware neural network using Altera FPGA chip-EP2C35F672C. The embedded Nios processor was used as the test bench. The test result showed that the SOPC Platform with hardware neural network is faster than the software implementation respectively and the accuracy of the design meets the requirement of system. The verified SOPC system can closely model real-world system, which will have wide applications in different areas such as pattern recognition, data mining and signal processing.

Infant health monitoring is crucial for early detection of potential health issues. Many existing solutions, while effective, are often costly and designed for clinical settings, making them less accessible for home use. Parents require an affordable, easy-to-use solution to monitor their infant’s vital signs, such as body temperature and pulse, in real time. The rapid development of wireless communication technologies and microcontroller systems like Programmable System-on-Chip (PSoC) provides a new opportunity to create effective, low-power, and cost-efficient health monitoring systems tailored for home use. This study focuses on developing a remote infant health monitoring system that integrates wireless data transmission to enable real-time monitoring by parents. The proposed system consists of three modules: On-Child-Device, Child-Device, and Parent-Device. The On-Child-Device, worn by the infant, measures vital signs using a thermistor and an infrared pulse sensor. The data is processed by a PSoC microcontroller and transmitted wirelessly to the Child-Device, which then forwards the information to the Parent-Device for display. The Parent-Device provides a user interface where parents can monitor real-time data, including alerts for abnormal readings. The system’s hardware is built using PSoC technology, offering flexibility in integrating sensors and communication protocols. Software development was carried out using the PSoC Designer environment, which allows for real-time data acquisition, error checking, and wireless communication management. Initial testing of the system demonstrated reliable performance in measuring and transmitting vital signs. The wireless communication between the modules showed minimal latency, with real-time data accurately displayed on the Parent-Device. The use of PSoC technology enabled efficient power consumption, allowing the system to operate continuously for extended periods without frequent battery replacements. The system's modular design also proved adaptable, allowing for potential integration of addition-al sensors in the future. Feedback from users highlighted the intuitive interface of the Parent-Device, making it accessible for non-technical users. However, challenges related to signal interference in certain environments were noted, suggesting the need for further optimization of the communication protocol. The developed remote infant health monitoring system offers a cost-effective, energy-efficient solution for home use. By utilizing PSoC technology, the system provides reliable real-time monitoring of vital signs, ensuring that parents can quickly respond to any health abnormalities. The wireless transmission and user-friendly interface make the system practical for everyday use, filling a significant gap in current infant health monitoring technologies. Future improvements will focus on enhancing the communication robustness and integrating additional health metrics to provide a more comprehensive monitoring solution. Keywords : Telemetric data, Parental device, Health monitoring, Temperature sensor, Pulse measurement, Programmable System on Chip

This paper discusses the design and implementation of a wireless sensor node using a Programmable System on Chip (PSoC). The main aim of this paper is to highlight the use and need of a low cost system for monitoring various parameters where human presence is prohibited. The system was implemented using a PSoC 3 device and transceivers CC2500 RF wireless module.

Proposed wireless sensor node is a highly flexible and programmable system on chip (PSoC) architecture along with integrated RF radio chip, which can be adapted to any IEEE 802.15.4 standard based protocol, working at the band of 2.4GHz.This can be accompanied by the RF antenna matched with the interface circuit for various kinds of sensors and peripherals to form a wireless sensor node.This can be very well used to form a wireless sensor network in different domains.This proposed methodology can be used for specific application for improving the WSN stability and performance.This article will mainly present the design of wireless sensor nodes based on PSoC and CyFi radio chip, including the application specific antenna and hardware design for the system on chip for the sensor node and the simple introduction of the application domain.The proposed nodes are used with a special antenna and application based protocol for communication.This design has a better power handling and performing capacity.Further, we have implemented this for the wireless sensor node as well.

In order to solve the problem that it is difficult to detect the local ice layer debonding when the thermal protection system is working, an on-line ultrasonic detection method for the melting degree of interface between skin and ice layer based on the theory of ultrasonic transmission in multi-layer media was studied. A multi-layer medium acoustic model including skin, water film, ice water transition layer, ice layer and air layer is constructed. Ultrasonic pulse waves with different center frequencies are used as excitation sources, and the echo signals of multi-layer medium interface are obtained by using the numerical calculation. The ultrasonic signal processing algorithm for ice melting and debonding measurement is developed. The original echo signal is processed and the characteristic parameters of the echo signal of interface between skin and ice layer are extracted. The ultrasonic reflection coefficient of interface between skin and ice layer is proposed to evaluate the degree of ice melting. The ultrasonic ice detection system was built, and the low-temperature ultrasonic sensor was designed and fabricated. The ability of the system to measure the degree of ice melting under the action of electric heating was verified in the low-temperature environment. The ultrasonic ice detection system was built, and the low-temperature ultrasonic sensor was designed and fabricated. The ability of the system to measure the degree of ice melting under the action of electric heating was verified in the low-temperature environment. The theoretical results show that when the ice on the skin melts and produces a thin water film, the degree of ice melting can be reflected by the change of ultrasonic reflection coefficient at the skin-attachment interface. In this paper, the ultrasonic reflection coefficient more than 0.8 is used as the criterion of ice melting. With the increasing of center frequency of the ultrasonic signal, the thinner water film can be identified. The identification thickness of the water film corresponding to 7.5 MHz center frequency signal is 10 μm. The experimental results show that under the conditions of clear ice, mixed ice and frost ice, the ultrasonic detection system can out-put the ice layer debonding signal at the initial stage of electric heating. The propagation characteristics of ultrasonic pulse wave of interface between skin and ice layer in the thermal protection are preliminarily explored. The present method for detecting the degree of ice melting is expected to further reduce the energy consumption of thermal protection.

Electrical impedance tomography is a recently established technique by which impedance of an object is measured data from the surface of the object, and a numerically simulated reconstruction of the phantom image can be obtained. The EIT experiment presented here used a phantom with 16 electrodes attached to the surface. When different current pulse applied across the phantom and potential are measured over all the electrode pairs. This imaging technique based on boundary or surface voltage is measured when the different current pattern is injected into it. For current pulse, we are creating a voltage controlled current source. It is a combination of wave generator and voltage to current converter and current position and measuring voltage is calculating using the created Control Unit or PSOC (Programmable system on chip) based EIT system. After that image reconstructing of the cross-sectional image of resistivity requires sufficient data collection by (Finite element method) FEM method and the EIDORs toolkit package of Matlab. FEM is a technique which helps in the creation of the image with EIDORs toolkit. It includes graphical mesh method linear and non-linear method using vector technique. The objective of the EIDORs toolkit was to produce an image from electrical impedance data and finally in the last phase 2-Dimensional image is obtained.

Conventional wearable sensors are mainly used to detect the physiological and activity information of individuals who wear them, but fail to perceive the information of the surrounding environment. This paper presents a wearable thermal sensing system to detect and perceive the information of surrounding human subjects. The proposed system is developed based on a pyroelectric infrared sensor. Such a sensor system aims to provide surrounding information to blind people and people with weak visual capability to help them adapt to the environment and avoid collision. In order to achieve this goal, a low-cost, low-data-throughput binary sampling and analyzing scheme is proposed. We also developed a conditioning sensing circuit with a low-noise signal amplifier and programmable system on chip (PSoC) to adjust the amplification gain. Three statistical features in information space are extracted to recognize static humans and human scenarios in indoor environments. The results demonstrate that the proposed wearable thermal sensing system and binary statistical analysis method are efficient in static human detection and human scenario perception.

The high performance of control systems essentially depends on the accuracy of the readable information which make embedded systems more effective by the execution of any instruction. But the universe is full of random information that can be described as chaos. In one hand, soft computing can present a perfect solution for random activities in control systems. It adds a new point of view and optimized one for the creation of new software approaches for control systems. In the other hand, FPGA (Field Programmable Gate Array) is a suitable hardware platform to apply these new ideas, but we will choose PSoC (Programmable System on Chip) which is a revolutionary programmable system that can create a hall different one every time. In this paper, we have tried theoretically, to combine these two aspects to come up with a hardware-software co-design by finding ways to translate soft computing aspects such as fuzzy logic algorithm: the surface polynomial modeling, to hardware programmable blocks.

The paper presents an impedance measurement method using a particular sampling method which is an alternative to DFT calculation. The method uses a sine excitation signal and sampling response signals proportional to current flowing through and voltage across the measured impedance. The object impedance is calculated without using Fourier transform. The method was first evaluated in MATLAB by means of simulation. The method was then practically verified in a constructed simple impedance measurement instrument based on a PSoC (Programmable System on Chip). The obtained calculation simplification recommends the method for implementation in simple portable impedance analyzers destined for operation in the field or embedding in sensors.

This paper discusses a FPGA-PSOC interface to be used as a lab platform in engineering education. We selected the Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) in the Programmable System on Chip (PSoC) device to externally interface with a Spartan 3E FPGA. Implementation on the FPGA was done using VHDL while analysis and experiments were performed to test for accuracy and speed. Results show that there was promise in using the interface and combination of the two devices for future teaching platforms with errors found to be sub 8% in both the ADC and DAC interfaces.

The Advanced Encryption Standard (AES) is a widely adopted symmetric-key cryptographic algorithm crucial for secure encryption and decryption. However, traditional hardware implementations of AES, such as Serial/Serial, Parallel/Serial, and Parallel/Pipelined architectures, encounter challenges related to resource utilization, execution time, and optimization. These architectures often present trade-offs between performance, area occupancy, and security. To overcome these limitations and enhance cryptographic security, an optimized FPGA-based solution is essential, particularly for high-performance applications that require both speed and robust security. This paper presents an optimized implementation of AES on an FPGA, integrating the Fuzzy Q-value Self-guided Regularized Structure Retention Generative Kepler’s Adversarial Transformer Network (FQSR-GKATN) to improve security and efficiency. The proposed method enhances critical AES transformations, such as SubBytes and MixColumns, by incorporating fuzzy Q-values for regularization, self-guided structuring for adaptive learning, and a retention mechanism to optimize resource usage. When implemented in hybrid cryptosystems like AES on FPGA PSoC (Programmable System on Chip), this architecture accelerates execution time and ensures improved security while optimizing resource consumption. The implementation achieves a balance between performance, throughput 97.87 Mbps, power consumption as 0.003 W, and security 99%, making it suitable for high-security cryptographic applications.

The ongoing trend in technology made home appliances and electronic devices connect to the Internet. However, an issue on energy efficiency is still a big problem to different countries although these technologies were used. Recently, the European Commission introduced the use of Power Line Communications (PLC) in which data is being transmitted through power lines as a preparation for transition from the Electric Grid to a new concept Smart Grid. PLC being a new wired protocol is still under development to communicate with other protocols including wireless protocol for seamless connection. The study focuses on interconnecting ZigBee wireless protocol to the said wired protocol by developing a gateway to convert their protocols into one common protocol. A method used in converting protocols includes varying the PLC's Programmable System on Chip (PSoC) into a computer architecture which enables Universal Asynchronous Receiver/Transmitted (UART) communication to successfully interconnect with ZigBee. The said interconnection is applied on a fuzzy logic controlled light system in which transmission test and power consumption was evaluated. The results of the analysis were presented to which they can be used as a guide for interconnecting other protocols with PLC.

In this study, we applied FDTR techniques to ultrasonic pulse-echo systems. To validate the system’s effectiveness, we compared SNR performance against theoretical values using contact pulse-echo systems. Experiments were conducted by varying the code length and the distance of inspected holes in metallic samples. The results demonstrated that holes in truncated ranges were detectable across all code lengths. Additionally, longer code lengths yielded higher SNR performance for holes in untruncated ranges. These findings indicate that applying FDTR techniques to ultrasonic pulse-echo testing effectively removes the limitations imposed by code length and significantly improves SNR performance. In radar applications, this issue has been addressed using full decoding of truncated ranges (FDTR) techniques, which enable decoding of received echoes in truncated ranges and eliminate the constraints associated with long coded excitations. Complementary code pairs are often employed as transmit waveforms in pulse compression systems because they produce no sidelobes under ideal conditions, enabling high SNR performance. While longer coded excitations improve SNR, decoding complementary code pairs requires received echoes of the same length. Consequently, for a code length of NNN, the first N−1N-1N−1 sampled ranges (truncated ranges) typically fail to decode. This limitation restricts the code length and, therefore, the extent of compression for observing nearby targets. Abstract: Achieving a high signal-to-noise ratio (SNR) in ultrasonic testing is crucial, and various methods have been developed to enhance it. One such method is pulse compression, which involves calculating correlation functions to improve axial resolution and SNR. This technique has been widely used for decades in radar, sonar, and ultrasonic systems.