Optimized AES Cryptosystem on FPGA Using FQSR-KAT Network for Enhanced Security and Performance

The wide acceptability of Advanced Encryption Standard (AES) as the most efficient of all of the symmetric cryptographic techniques has further opened it up to more attacks. Efforts that were aimed at securing information while using AES is still being undermined by the activities of attackers This has further necessitated the need for researchers to come up with ways of enhancing the strength of AES. This article presents an enhanced AES algorithm that was achieved by modifying its SubBytes and ShiftRows transformations. The SubBytes transformation is modified to be round key dependent, while the ShiftRows transformation is randomized. The rationale behind the modification is to make the two transformations round key dependent, so that a single bit change in the key will produce a significant change in the cipher text. The conventional and modified AES algorithms are both implemented and evaluated in terms avalanche effect and execution time. The modified AES algorithm achieved an avalanche effect of 57.81% as compared to 50.78 recorded with the conventional AES. However, with 16, 32, 64, and 128 plain text bytes, the modified AES recorded an execution time of 0.18, 0.31, 0.46, and 0.59 ms, respectively. This is slightly higher than the results obtained with the conventional AES. Though a slightly higher execution time in milliseconds was recorded with the modified AES, the improved encryption and decryption strength via the avalanche effects measured is a desirable feat.

nowadays, data stored in mobile phones become often vulnerable that it is stolen by hackers. More than 50% of mobile users do not encrypt their mobile phones which might result in stealing data when mobile is hacked or stolen. Android encryption is used in android mobiles. The encryption algorithm used is 128 Advanced Encryption Standard (AES) with cipher-block chaining (CBC) and SHA256.In this paper, the data in mobile is encrypted using multiple algorithms(AES, Salsa20, fernet). This method is called hybrid encryption. The data is split and encrypted with multiple algorithms. The selected file to be encrypted is divided into three segments and encrypted with AES, Salsa20, and Fernet algorithms. Then the private keys are encrypted with the RSA (Rivest-Shamir-Adleman) algorithm. The RSA cipher file is stored in phone storage. For decryption, the RSA cipher file is obtained and the responding keys are obtained. With the keys, the AES, Salsa20, Fernet algorithms decrypt the responding encrypted segments. The decrypted segments are combined and the original file is obtained. Then the file is stored in the device.

Since embedded systems have such a wide range of applications in today's time, there is a pressing need to meet the design requirements such as power consumption, cost, time to market, flexibility and robustness. Power consumption by embedded systems is a particularly critical issue. This paper is a starting point for understanding power aware design methodologies, and it reviews the various techniques of designing power efficient embedded systems using Programmable System on Chip (PSoC). PSoC is a true programmable embedded SoC (System on Chip) which integrates configurable analog and digital components, memory and a microcontroller on a single chip thus providing high level of flexibility and configurability.

Hardware Trojans pose a significant threat to the security and integrity of cryptographic systems, particularly in Advanced Encryption Standard (AES) implementations, which are widely used in securing sensitive data. These malicious modifications to integrated circuits (ICs) can compromise the confidentiality and reliability of AES cryptographic operations by introducing covert backdoors, information leakage channels, or functional disruptions. Hardware Trojans are typically designed to evade detection during design-time validation and post-manufacturing testing, often activating only under specific triggers such as rare input patterns or environmental conditions. In AES systems, Trojans can manipulate the encryption process by leaking secret keys through side-channel information such as power consumption, timing variations, or electromagnetic emissions. Some Trojans directly alter the encryption algorithm, weakening the cryptographic strength and rendering encrypted data vulnerable to attacks. Attackers may also embed Trojans at the Register Transfer Level (RTL) or gate-level design, leveraging the inherent complexity of AES circuits to conceal their presence. Detection and mitigation of hardware Trojans in AES implementations are challenging due to their stealthy nature. Techniques such as side-channel analysis, functional verification, and static code analysis have been developed, but sophisticated Trojans often bypass these methods. Advanced countermeasures include runtime monitoring, hardware obfuscation, and Trojan-resilient design methodologies. This paper explores the implications of hardware Trojans in AES cryptographic systems, analysing their design, potential attack vectors, and impacts on data security. Furthermore, it discusses state-of-the-art detection and prevention techniques, highlighting gaps and future research directions. Given the critical role of AES in securing financial, military, and consumer data, addressing the hardware Trojan threat is paramount to ensuring trust in cryptographic hardware and safeguarding against adversarial exploitation.

Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between the processor and the memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and non-invasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for advanced encryption standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domain-wall nanowires. The entire encryption process can be completed within a homogeneous, high-density, and standby-power-free non-volatile spintronic-based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowire-based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with an insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by the orders of magnitude compared with existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/b, which is $5\times $ and $3\times $ better than the CMOS ASIC and memristive CMOL-based implementations, respectively. Under the same area budget, the proposed DW-AES achieves $4.6\times $ higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to $11\times $ for pipelined DW-AES at the expense of doubling the power consumption.

With the increasing reliance on digital communication and data storage, the need for secure encryption and decryption techniques has become paramount. This abstract presents a study on the application of the Advanced Encryption Standard (AES) with a 128-bit key algorithm for the encryption and decryption of both images and text. AES is a widely adopted symmetric encryption algorithm known for its robust security and efficiency. The key length of 128 bits ensures a large key space, making brute-force attacks computationally infeasible. In this study, we propose a methodology for encrypting and decrypting both images and text using AES with a 128-bit key algorithm.

Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

The Advanced Encryption Standard (AES) is a newly accepted secret key cryptographic standard for secure transfer of blocks of data. Among different transformations, the SubBytes transformation is the most expensive one in terms of the chip area and the power consumption in the hardware implementation of the AES. It consists of 16 S-boxes and hence the hardware optimization of the S-box is critical to reach a low-cost AES. In this paper, we present a low-cost S-box for the AES. Instead of using look-up tables for implementing the S-box, logic gate implementation based on a previously known low-complexity composite field using normal basis is utilized. Then, we present improved formulations for the inversion in the sub-fields within the S-box to reduce the area complexity of the implementations. After analyzing the complexities of the new architecture, we compare the ASIC implementation of the proposed S-box using 0:18µ CMOS technology with the previous ones. It is shown that the presented scheme has the lowest power consumption and area compared to its counterparts available in the open literature.

The Advanced Encryption Standard (AES), also known as a specification for the encryption of electronic data. AES is comparatively highly secure and more efficient than well-known other cryptographic algorithms and existing Data Encryption Standard (DES). This work is focused in analyzing selecting valuable research publications on AES. This also discusses some machine learning techniques such as artificial neural network (ANN) used to protect side channel attack for images. Besides this, many other recent developments such as effective differential power analysis (DPA) technique and hybrid encryption algorithm using LZW have been discussed and analyzed in details. Finally, the paper concludes with a systematic analysis of different types of attacks on AES and some future research aspects in this context. Finally, this work also proposes a new model for attack detection in AES.

As the amount of data is increasing rapidly, its storage and security issues also increase. Hadoop is currently a popular framework for big data storage and processing. Since, security is not a primary consideration in Hadoop when it was initially developed makes the data stored in Hadoop distributed file system (HDFS) vulnerable to attacks. For protecting these data, numerous encryption techniques has been developed. This paper analyses and presents a comparison on advanced encryption standard (AES), a symmetric cipher and Rivest-Shamir-Adleman (RSA), an asymmetric cipher cryptographic algorithms. Finally, this paper proposes a hybrid method that combines both RSA and AES technique to improve the performance of encryption-decryption on HDFS files and thereby increases the security of big data in Hadoop framework. The proposed technique is found to be feasible and is able to enhance the confidentiality of HDFS files stored in Hadoop framework and is also able to overcome the limitations when using the AES encryption technique alone.KeywordsBig dataData securityHadoopHDFSEncryptionDecryptionAESRSAHybrid

With today's development and expansion of networks and internet-connected devices, information security is an issue of increasing concern. Confidentiality is one of the focuses in network security for digital communication systems, where large data blocks go through a cryptographic algorithm with a cipher key that increases the security and complexity of the output ciphertext. For the past several years, multiple security algorithms have been developed and utilized in the data encryption process, such as the Data Encryption Standard (DES), Triple Data Encryption Standard (3DES), and the current one, designated by the U.S. National Institute of Standards and Technology (NIST), the Advanced Encryption Standard (AES). AES is a symmetric encryption algorithm that has a minimum input data block size of 128-bits which undergo a series of permutations, substitutions, and digital logic operations over several rounds. Encryption algorithms are always improving on ciphertext complexity, required hardware storage allocation, and execution time. Field Programmable Gate Arrays (FPGA's) are a hardware alternative for encryption algorithm implementation because, although the logic units in it are fixed, the functions and interconnections between them are based on the user's design which allow for improvement. The research presented focuses on the development and analysis of an efficient AES-128 Mix Columns algorithm implementation, utilized in the data block encryption rounds, on an Altera Cyclone IV FPGA using the Intel Quartus II software and Verilog Hardware Description Language.

Parametric equalization is often used to achieve a desired response from an audio transmitter, but is rarely applied to ultrasonic transducer systems. The ability of a broadband ultrasonic transmission and reception system to adapt its frequency and time domain response to changing acoustic conditions would be a distinct advantage in certain applications. Ultrasonic remote monitoring systems would benefit significantly from this ability, as signal levels could be minimized and consequentially the transmitter power consumption decreased. This work presents a real-time adaptive ultrasonic parametric equalizer using optimization driven Matlab code to control the coefficients of a switched capacitor filter network implemented in a Cypress PSOC (Programmable System On a Chip). In this work, adaptive parametric magnitude equalization of a through-transmission ultrasonic system using CUTs (Capacitive Ultrasonic Transducers) has been achieved in real time by tracking a desired SNR (signal to noise ratio) across the operational frequency spectrum. A Matlab general radial basis function (GRBF) artificial neural network (ANN) was developed to control the equalization filter coefficients based on the received frequency response data. The adaptive parametric equaliser adjusts the magnitude of the driving signal to maintain the desired SNR as closely as possible. The neural network was trained using PSO (Particle Swarm Optimization) back-propagation, based on a state space model of the system developed from frequency response data. The developed equalization circuitry, which is switched capacitor based and was fully implemented on the PSOC, is also described.

In this paper four simple but very effective image enhancement technique is implemented in a digital configurable block on Programmable System on Chip (PSoC). This is done by converting a 2D gray image matrix to 1D vector and send it to PSoC5 LP Universal Asynchronous Receiver Transmitter (UART).The UART is communicating with a Verilog component which use Universal Digital Block Array (UDB) for implementing image enhancement algorithms. For implementing enhancement algorithm very simple Verilog components are developed by using Cypress PSoC Creator 2.2, It includes adder, subtracter, multiplier, 8 bit comparator, and multiplexer. Verilog components for constant values are also developed. Enhancement algorithms are implemented with the integration of arithmetic, logical and constant Verilog components.

A modified XXTEA “M-XXTEA” symmetric block cipher that has a simple construction compared to the advanced encryption standard (AES) is proposed. It is efficient for protecting limited-resource devices such as IoT smart devices. The M-XXTEA will be able to achieve confidentiality during transmission of data over the internet. Since the original XXTEA was vulnerable against key-related and chosen-plaintext attacks. Therefore, this paper introduces a new and robust version of the original XXTEA by employing an improved S-box to enhance security to overcome such types of attacks. Besides, the M-XXTEA is coupled with a chaotic key generator system adding a layer of security achieving the idea behind the one-time pad. The cipher keys are dynamically changing for each block of plaintext when encrypted. Thus, it provides a more robust security mechanism than the original XXTEA and the AES. Besides enhancing data security, the M-XXTEA can function with different sizes of text blocks and with different key sizes. Several experiments are implemented to compare the performance of the M-XXTEA with the original XXTEA and with the AES. Results show that the M-XXTEA encryption and decryption time efficiencies outperform AES by 60%. Besides, the M-XXTEA achieves speed efficiency 57% better than the AES. It can be used efficiently for protecting IoT smart devices in the industry, and e-health systems, and smart cities.

Infant health monitoring is crucial for early detection of potential health issues. Many existing solutions, while effective, are often costly and designed for clinical settings, making them less accessible for home use. Parents require an affordable, easy-to-use solution to monitor their infant’s vital signs, such as body temperature and pulse, in real time. The rapid development of wireless communication technologies and microcontroller systems like Programmable System-on-Chip (PSoC) provides a new opportunity to create effective, low-power, and cost-efficient health monitoring systems tailored for home use. This study focuses on developing a remote infant health monitoring system that integrates wireless data transmission to enable real-time monitoring by parents. The proposed system consists of three modules: On-Child-Device, Child-Device, and Parent-Device. The On-Child-Device, worn by the infant, measures vital signs using a thermistor and an infrared pulse sensor. The data is processed by a PSoC microcontroller and transmitted wirelessly to the Child-Device, which then forwards the information to the Parent-Device for display. The Parent-Device provides a user interface where parents can monitor real-time data, including alerts for abnormal readings. The system’s hardware is built using PSoC technology, offering flexibility in integrating sensors and communication protocols. Software development was carried out using the PSoC Designer environment, which allows for real-time data acquisition, error checking, and wireless communication management. Initial testing of the system demonstrated reliable performance in measuring and transmitting vital signs. The wireless communication between the modules showed minimal latency, with real-time data accurately displayed on the Parent-Device. The use of PSoC technology enabled efficient power consumption, allowing the system to operate continuously for extended periods without frequent battery replacements. The system's modular design also proved adaptable, allowing for potential integration of addition-al sensors in the future. Feedback from users highlighted the intuitive interface of the Parent-Device, making it accessible for non-technical users. However, challenges related to signal interference in certain environments were noted, suggesting the need for further optimization of the communication protocol. The developed remote infant health monitoring system offers a cost-effective, energy-efficient solution for home use. By utilizing PSoC technology, the system provides reliable real-time monitoring of vital signs, ensuring that parents can quickly respond to any health abnormalities. The wireless transmission and user-friendly interface make the system practical for everyday use, filling a significant gap in current infant health monitoring technologies. Future improvements will focus on enhancing the communication robustness and integrating additional health metrics to provide a more comprehensive monitoring solution. Keywords : Telemetric data, Parental device, Health monitoring, Temperature sensor, Pulse measurement, Programmable System on Chip