Static Human Detection and Scenario Recognition via Wearable Thermal Sensing System

Since embedded systems have such a wide range of applications in today's time, there is a pressing need to meet the design requirements such as power consumption, cost, time to market, flexibility and robustness. Power consumption by embedded systems is a particularly critical issue. This paper is a starting point for understanding power aware design methodologies, and it reviews the various techniques of designing power efficient embedded systems using Programmable System on Chip (PSoC). PSoC is a true programmable embedded SoC (System on Chip) which integrates configurable analog and digital components, memory and a microcontroller on a single chip thus providing high level of flexibility and configurability.

In this paper four simple but very effective image enhancement technique is implemented in a digital configurable block on Programmable System on Chip (PSoC). This is done by converting a 2D gray image matrix to 1D vector and send it to PSoC5 LP Universal Asynchronous Receiver Transmitter (UART).The UART is communicating with a Verilog component which use Universal Digital Block Array (UDB) for implementing image enhancement algorithms. For implementing enhancement algorithm very simple Verilog components are developed by using Cypress PSoC Creator 2.2, It includes adder, subtracter, multiplier, 8 bit comparator, and multiplexer. Verilog components for constant values are also developed. Enhancement algorithms are implemented with the integration of arithmetic, logical and constant Verilog components.

Parametric equalization is often used to achieve a desired response from an audio transmitter, but is rarely applied to ultrasonic transducer systems. The ability of a broadband ultrasonic transmission and reception system to adapt its frequency and time domain response to changing acoustic conditions would be a distinct advantage in certain applications. Ultrasonic remote monitoring systems would benefit significantly from this ability, as signal levels could be minimized and consequentially the transmitter power consumption decreased. This work presents a real-time adaptive ultrasonic parametric equalizer using optimization driven Matlab code to control the coefficients of a switched capacitor filter network implemented in a Cypress PSOC (Programmable System On a Chip). In this work, adaptive parametric magnitude equalization of a through-transmission ultrasonic system using CUTs (Capacitive Ultrasonic Transducers) has been achieved in real time by tracking a desired SNR (signal to noise ratio) across the operational frequency spectrum. A Matlab general radial basis function (GRBF) artificial neural network (ANN) was developed to control the equalization filter coefficients based on the received frequency response data. The adaptive parametric equaliser adjusts the magnitude of the driving signal to maintain the desired SNR as closely as possible. The neural network was trained using PSO (Particle Swarm Optimization) back-propagation, based on a state space model of the system developed from frequency response data. The developed equalization circuitry, which is switched capacitor based and was fully implemented on the PSOC, is also described.

Infant health monitoring is crucial for early detection of potential health issues. Many existing solutions, while effective, are often costly and designed for clinical settings, making them less accessible for home use. Parents require an affordable, easy-to-use solution to monitor their infant’s vital signs, such as body temperature and pulse, in real time. The rapid development of wireless communication technologies and microcontroller systems like Programmable System-on-Chip (PSoC) provides a new opportunity to create effective, low-power, and cost-efficient health monitoring systems tailored for home use. This study focuses on developing a remote infant health monitoring system that integrates wireless data transmission to enable real-time monitoring by parents. The proposed system consists of three modules: On-Child-Device, Child-Device, and Parent-Device. The On-Child-Device, worn by the infant, measures vital signs using a thermistor and an infrared pulse sensor. The data is processed by a PSoC microcontroller and transmitted wirelessly to the Child-Device, which then forwards the information to the Parent-Device for display. The Parent-Device provides a user interface where parents can monitor real-time data, including alerts for abnormal readings. The system’s hardware is built using PSoC technology, offering flexibility in integrating sensors and communication protocols. Software development was carried out using the PSoC Designer environment, which allows for real-time data acquisition, error checking, and wireless communication management. Initial testing of the system demonstrated reliable performance in measuring and transmitting vital signs. The wireless communication between the modules showed minimal latency, with real-time data accurately displayed on the Parent-Device. The use of PSoC technology enabled efficient power consumption, allowing the system to operate continuously for extended periods without frequent battery replacements. The system's modular design also proved adaptable, allowing for potential integration of addition-al sensors in the future. Feedback from users highlighted the intuitive interface of the Parent-Device, making it accessible for non-technical users. However, challenges related to signal interference in certain environments were noted, suggesting the need for further optimization of the communication protocol. The developed remote infant health monitoring system offers a cost-effective, energy-efficient solution for home use. By utilizing PSoC technology, the system provides reliable real-time monitoring of vital signs, ensuring that parents can quickly respond to any health abnormalities. The wireless transmission and user-friendly interface make the system practical for everyday use, filling a significant gap in current infant health monitoring technologies. Future improvements will focus on enhancing the communication robustness and integrating additional health metrics to provide a more comprehensive monitoring solution. Keywords : Telemetric data, Parental device, Health monitoring, Temperature sensor, Pulse measurement, Programmable System on Chip

SOPC (System on Programmable Chip) is an on-chip programmable system based on large scale Field Programmable Arrays (FPGAs). This paper presented an implementation of an SOPC system with a custom hardware neural network using Altera FPGA chip-EP2C35F672C. The embedded Nios processor was used as the test bench. The test result showed that the SOPC Platform with hardware neural network is faster than the software implementation respectively and the accuracy of the design meets the requirement of system. The verified SOPC system can closely model real-world system, which will have wide applications in different areas such as pattern recognition, data mining and signal processing.

This paper discusses the design and implementation of a wireless sensor node using a Programmable System on Chip (PSoC). The main aim of this paper is to highlight the use and need of a low cost system for monitoring various parameters where human presence is prohibited. The system was implemented using a PSoC 3 device and transceivers CC2500 RF wireless module.

Proposed wireless sensor node is a highly flexible and programmable system on chip (PSoC) architecture along with integrated RF radio chip, which can be adapted to any IEEE 802.15.4 standard based protocol, working at the band of 2.4GHz.This can be accompanied by the RF antenna matched with the interface circuit for various kinds of sensors and peripherals to form a wireless sensor node.This can be very well used to form a wireless sensor network in different domains.This proposed methodology can be used for specific application for improving the WSN stability and performance.This article will mainly present the design of wireless sensor nodes based on PSoC and CyFi radio chip, including the application specific antenna and hardware design for the system on chip for the sensor node and the simple introduction of the application domain.The proposed nodes are used with a special antenna and application based protocol for communication.This design has a better power handling and performing capacity.Further, we have implemented this for the wireless sensor node as well.

Electrical impedance tomography is a recently established technique by which impedance of an object is measured data from the surface of the object, and a numerically simulated reconstruction of the phantom image can be obtained. The EIT experiment presented here used a phantom with 16 electrodes attached to the surface. When different current pulse applied across the phantom and potential are measured over all the electrode pairs. This imaging technique based on boundary or surface voltage is measured when the different current pattern is injected into it. For current pulse, we are creating a voltage controlled current source. It is a combination of wave generator and voltage to current converter and current position and measuring voltage is calculating using the created Control Unit or PSOC (Programmable system on chip) based EIT system. After that image reconstructing of the cross-sectional image of resistivity requires sufficient data collection by (Finite element method) FEM method and the EIDORs toolkit package of Matlab. FEM is a technique which helps in the creation of the image with EIDORs toolkit. It includes graphical mesh method linear and non-linear method using vector technique. The objective of the EIDORs toolkit was to produce an image from electrical impedance data and finally in the last phase 2-Dimensional image is obtained.

The high performance of control systems essentially depends on the accuracy of the readable information which make embedded systems more effective by the execution of any instruction. But the universe is full of random information that can be described as chaos. In one hand, soft computing can present a perfect solution for random activities in control systems. It adds a new point of view and optimized one for the creation of new software approaches for control systems. In the other hand, FPGA (Field Programmable Gate Array) is a suitable hardware platform to apply these new ideas, but we will choose PSoC (Programmable System on Chip) which is a revolutionary programmable system that can create a hall different one every time. In this paper, we have tried theoretically, to combine these two aspects to come up with a hardware-software co-design by finding ways to translate soft computing aspects such as fuzzy logic algorithm: the surface polynomial modeling, to hardware programmable blocks.

The paper presents an impedance measurement method using a particular sampling method which is an alternative to DFT calculation. The method uses a sine excitation signal and sampling response signals proportional to current flowing through and voltage across the measured impedance. The object impedance is calculated without using Fourier transform. The method was first evaluated in MATLAB by means of simulation. The method was then practically verified in a constructed simple impedance measurement instrument based on a PSoC (Programmable System on Chip). The obtained calculation simplification recommends the method for implementation in simple portable impedance analyzers destined for operation in the field or embedding in sensors.

This paper discusses a FPGA-PSOC interface to be used as a lab platform in engineering education. We selected the Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) in the Programmable System on Chip (PSoC) device to externally interface with a Spartan 3E FPGA. Implementation on the FPGA was done using VHDL while analysis and experiments were performed to test for accuracy and speed. Results show that there was promise in using the interface and combination of the two devices for future teaching platforms with errors found to be sub 8% in both the ADC and DAC interfaces.

The Advanced Encryption Standard (AES) is a widely adopted symmetric-key cryptographic algorithm crucial for secure encryption and decryption. However, traditional hardware implementations of AES, such as Serial/Serial, Parallel/Serial, and Parallel/Pipelined architectures, encounter challenges related to resource utilization, execution time, and optimization. These architectures often present trade-offs between performance, area occupancy, and security. To overcome these limitations and enhance cryptographic security, an optimized FPGA-based solution is essential, particularly for high-performance applications that require both speed and robust security. This paper presents an optimized implementation of AES on an FPGA, integrating the Fuzzy Q-value Self-guided Regularized Structure Retention Generative Kepler’s Adversarial Transformer Network (FQSR-GKATN) to improve security and efficiency. The proposed method enhances critical AES transformations, such as SubBytes and MixColumns, by incorporating fuzzy Q-values for regularization, self-guided structuring for adaptive learning, and a retention mechanism to optimize resource usage. When implemented in hybrid cryptosystems like AES on FPGA PSoC (Programmable System on Chip), this architecture accelerates execution time and ensures improved security while optimizing resource consumption. The implementation achieves a balance between performance, throughput 97.87 Mbps, power consumption as 0.003 W, and security 99%, making it suitable for high-security cryptographic applications.

The ongoing trend in technology made home appliances and electronic devices connect to the Internet. However, an issue on energy efficiency is still a big problem to different countries although these technologies were used. Recently, the European Commission introduced the use of Power Line Communications (PLC) in which data is being transmitted through power lines as a preparation for transition from the Electric Grid to a new concept Smart Grid. PLC being a new wired protocol is still under development to communicate with other protocols including wireless protocol for seamless connection. The study focuses on interconnecting ZigBee wireless protocol to the said wired protocol by developing a gateway to convert their protocols into one common protocol. A method used in converting protocols includes varying the PLC's Programmable System on Chip (PSoC) into a computer architecture which enables Universal Asynchronous Receiver/Transmitted (UART) communication to successfully interconnect with ZigBee. The said interconnection is applied on a fuzzy logic controlled light system in which transmission test and power consumption was evaluated. The results of the analysis were presented to which they can be used as a guide for interconnecting other protocols with PLC.

Isolated Speech recognition systems (ISRS) have been implemented using microprocessors, digital signal processors and FPGAs and have been reported in the literature. In this paper, the study and implementation of an ISRS using Cypress Programmable System on Chip (PSoC) is presented. For the implementation, PSoC5 containing the ARM Cortex-M3 CPU is used. Recognition performance is studied using three feature extraction techniques (Zero crossing, Zero crossing with end point detection and Zero crossing with end point detection and Cochlear filter) and minimum distance classifier. The ISRS is trained and tested using 10 utterances of three words. The performance is evaluated for utterances by both single speaker and multiple speaker. From this study, it is found that the system using the Zero crossing with end point detection and Cochlear filter gives the highest recognition accuracy of 80%and 70% respectively for the utterances by single speaker and multiple speakers. Higher recognition accuracy can be obtained using more robust feature extraction and classification techniques at the cost of increase in the computation complexity and storage space. The proposed ISRS has applications in voice operated robots, appliances and access control systems.

Wearable physiological monitoring systems have gained popularity in the recent years due to their ability to continuously monitor physiological signals, thereby making them suitable for home-healthcare applications. The electrocardiogram (ECG), phonocardiogram (PCG) and photoplethysmogram (PPG) signals have been studied and it has been observed that there is a correlation between the three signals. This paper proposes the development of a secure body area network (BAN), for a wearable physiological monitoring system. The BAN is composed of three nodes, for ECG, PPG and PCG signals. The peak–peak distances of these signals are calculated first, in the coordinator of BAN. The coordinator is designed in such a manner that signals from it are transmitted to a monitoring station, only if the difference between the peak–peak distances of both ECG-PPG signals and ECG-PCG signals fall below a threshold. The entire operation of the coordinator is implemented using a real-time processor, Cypress™ Programmable System on Chip (PSoC).