Software-defined radio design based on GALS architecture for FPGAs

This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-square-error MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact.

We summarize the security necessary for software defined radio (SDR) systems, and propose a flexible structure for security systems on SDR. We introduce a new electronic commerce scheme for SDR that utilizes the ability of SDR to switch between different security algorithms for electronic commerce. We evaluate the performance of the cryptographic algorithms used in electronic commerce on various platforms including SDR systems, as basic research toward the implementation of SDR.

Field Programmable Gated Array (FPGA) provides a way for developing system on chip reconfigurable modules with high performance. In this paper, FPGA architecture for recovering audio signals from digitally modulated frequency wave is proposed, which would be a starting point for developing an efficient Software Defined Radio (SDR) architecture. At the modulator and demodulator sections, a Digital Frequency Generator (DFG) is used for generating the carrier wave by exploiting the quarter wave symmetry of sine or cosine waves with dynamic range of more than 90dB. Digital Phase Locked Loop (DPLL) with DFG is used to demodulate the Frequency Modulated (FM)audio signals. Simulation and synthesis are done using Xilinx 13.1. The proposed architecture works around a frequency of 106MHz and uses 1.032 K equivalent gates when tested using XC3S1600E-4fg320, Spartan 3E board with power consumption of around 120mW.

The Lunar Augmented Navigation Service (LANS) is the lunar equivalent of GNSS for future lunar explorations. It offers users accurate position, navigation, and timing (PNT) capabilities on and around the Moon. The Augmented Forward Signal (AFS) is a standardized signal structure for LANS, and its recommended standard was published online on 7 February 2025. This work presents software-defined radio (SDR) implementations of the LANS AFS simulator and receiver, which were rapidly developed within a month of the signal specification release. Based on open-source GNSS software, including GPS-SDR-SIM and Pocket SDR, our system provides a valuable platform for future algorithm research and hardware-in-the-loop testing. The receiver can operate on embedded platforms, such as the Raspberry Pi 5, in real-time. This feature makes it suitable for lunar surface applications, where conventional PC-based SDR systems are impractical due to their size, weight, and power requirements. Our approach demonstrates how open-source SDR frameworks can be rapidly applied to emerging satellite navigation signals, even for extraterrestrial PNT applications.

In this paper a software-defined radio (SDR) implementation of a wireless transmitting (Tx) system is proposed. It is intended for real-time wireless transfer of time-critical control, diagnostics, and calibration data between a hardware-in-the-loop (HIL) test system and an automotive electronic control unit enabling novel HIL testing methods. The introduced SDR Tx system applies the wideband physical layer IEEE 802.11p and is designed for low Tx latency. Besides, it provides adaptivity in terms of a listen-before-talk mechanism that is mandatory required by the revised European spectrum regulations in the 2.4GHz industrial, scientific, and medical frequency band. Using hardware measurements concerning Tx latency and performance it is shown that the SDR Tx system offers an appropriate solution to evaluate the introduced real-time wireless application.

This paper is devoted to the software-defined radio (SDR) implementation of frequency modulated antipodal chaos shift keying (FM-ACSK) communication system. This novel and perspective class of spread-spectrum systems employs chaotic synchronization for the acquisition and tracking of the spreading signal and does not need resource-demanding cross-correlation usually employed for this purpose. This paper aims to present how to implement a full FM-ACSK communication system, including additional synchronization circuitry, using SDR and MATLAB Simulink. Moreover, for the first time, the performance of FM-ACSK in real conditions using over-the-air transmission between two SDRs is assessed. In the paper, it is shown that the presented class of the spread spectrum systems demonstrates good performance in low signal-to-noise ratio (SNR) conditions, and it is immune to large carrier frequency offset (CFO). The proposed solution fits well to low-speed long-range wireless sensor network (WSN) applications.

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

The Software-Defined Radio (SDR) concept was originally developed by the combined efforts of various research groups in the private and government organizations of the United States (US) in 1970s–1980s. The important ones to mention are the US Department of Defense Laboratory and a team at the Garland, Texas Division of E-Systems Inc. In 1991, Joe Mitola independently reinvented the term ‘Software Radio’ (SR) in cooperation with E-Systems as a plan to build a true software-based GSM transceiver (Mitola, Telesystems Conference, 1992). The SR platform essentially processes almost all the transceiver algorithms as software for a processor. This includes nearly all layers of transmission. However, an optimal implementation of physical layer is always challenging due to an enormous amount of mathematical computation. Over the period of time, many developmental changes occurred and an interesting feature of cognition was added to existing SDR platforms, thereby inventing the term ‘Cognitive Radio’. The main idea was to reduce over-sampling by the analog to digital converter, reduce on-chip processing and to target only the spectrum of interest. This book also touches the CR feature in the large SDR field in some of its selected chapters. Since, the very first few articles of J. Mitola, there has a been a tremendous amount of research work conducted in industry and academia. The evolution in SDRs is continuous with time and provides a number of excellent opportunities to researcher for exploration and to come up with their findings. The present day SDR implementations are such that the designers are focused mostly on the design of hardware and software, their interfacing and optimizations for varying architectural choices. It includes multiple cases of application-specific general-purpose acceleration platforms that are scalable, homogeneous and heterogeneous in nature while providing multiple programmable cores on a single chip computing system.

Due to the scarcity and high cost of satellite frequency spectrum, it is very important to utilize the available spectrum as efficiently as possible. The efficient usage of the spectrum in the satellite return link is a challenging task, especially if multiple users are present. In previous works Multi-User Detection (MUD) techniques have been widely studied to increase the spectral efficiency of the satellite return link. However, due to the high computational complexity and its sensitivity to synchronization and channel estimation errors, only few implementations of MUD for satellite communications exist. In this paper a novel Graphics Processing Unit (GPU)-based Software Defined Radio (SDR) implementation of a MUD receiver for transparent satellite return link is presented, which uses iterative channel estimation and decoding. The implementation can cope with the presence of strong phase noise. In addition to its high flexibility and low cost, with the GPU acceleration our SDR MUD receiver implementation achieves a decoding throughput of 270 Kbps using a single GPU card.

Progress made in optical references, including ultrastable Fabry-Perot cavities, optical frequency combs, and optical atomic clocks, has driven the need for ultrastable optical fiber networks. Telecom-wavelength ultrapure optical signal transport has been demonstrated on distances ranging from the laboratory scale to the continental scale. In this article, we present a Doppler-cancellation setup based on a digital phase-locked loop (PLL) for ultrastable optical signal dissemination over fiber. The optical phase stabilization setup is based on a usual heterodyne Michelson-interferometer setup, while the software-defined radio (SDR) implementation of the PLL is based on a compact commercial board embedding a field-programmable gate array and analog-to-digital and digital-to-analog converters. Using three different configurations, including an undersampling method, we demonstrate a 20-m-long fiber link with residual fractional frequency instability as low as 10-18 at 1000 s and optical phase noise of -70 dBc/Hz at 1 Hz with a telecom frequency carrier.

The study developed and evaluated the performance of an improved algorithm to demodulate sampled data frequency modulation (FM) signals in typical field programmable gate array (FPGA) - based software defined radios (SDR). An algorithm, based on the modification of a standard differentiate-divide FM demodulator was developed. The hardware resources requirement and the input noise suppression ability of the developed algorithm were investigated. The demodulator developed requires a quarter of the hardware resources needed by conventional differentiate-divide FM demodulators. The output signal to noise ratio (SNR) of the developed demodulator is lower than that of the standard differentiate divide-demodulator when the input carrier to noise ratio (CNR) is less than 45 decibels. The SNR plot of the developed demodulator is more linear, compared to that of the original differentiate-divide demodulator. This implies that the developed demodulator can be implemented using smaller sized FPGAs, thus reducing cost and the power dissipated. The small silicon area occupied by the demodulator gives room for instantiation of more demodulators and other signal processing units on the same FPGA chip

The current and projected rapid increase in usage of the radio frequency identification (RFID) tags will yield new uses and applications in an Internet of things (IoT) environment. This chapter will discuss the implementation of software-defined radio (SDR) to aggregate, analytically process, and efficiently transmit data from RFID tags through a satellite backhaul solution. In the infrastructure proposed below, the first layer SDR aggregates RFID data at a tower level, the second layer SDR aggregates tower data at a low Earth orbit (LEO) satellite level, and then this aggregated data are backhauled to the gateway for the third layer SDR processing and data analytics. This chapter will discuss the RFID/SDR current and future capabilities, SDR design trades, RFID/ SDR system prototype test results, and satellite implementation scenarios.

The implementation of software-defined radio necessitates a versatile radio frequency (RF) front-end that can support multiple standards in different frequency bands. This article presents the state-of-the-art multiband and wideband mixers in the context of different receiver architectures suitable for software-defined radio (SDR). Wideband and multiband mixer designs reported in the literature are categorized on the basis of their circuit architecture. This study tabulates the results of mixer designs with an emphasis on noise figure (NF), conversion gain (CG), linearity, and image rejection ratio. The best parameters reported in the comparison are 68–84 dB of CG, 3.2 dB of NF, 2.5 mW of power consumption, 12.5 dBm of third-order input intercept point, and 0.015 mm2 of area at different frequencies. The study also discusses the design challenges and techniques to overcome those issues. The article concludes with the summary and prospective developments for SDR architectures.

"Radio Design in Nanometer Technologies" addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. To that end, the book contains three parts: Part 1 is a general part discussing current and future wireless networks, chipset evolution over the past decade and ending with a discussion on radio requirements for software defined radio(SDR). Part 2 will focus on the digital baseband of a wireless chip set, flexible DSP cores for multi-standard wireless platforms and system-on-chip SoC implementation and design flow issues. Part 3 will be devoted to radio design issues starting at the transceiver level and going down to discuss critical issues facing design of future multi band multi standard radios for emerging wireless standards such as UMTS, WiMaX, MIMO and WLAN in a way that is consistent with the prevailing vision of SDR. As such, the book is the first volume that looks at the integrated radio design problem as a 'piece of a big puzzle', namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today's increasingly complex wireless systems

Efficient and effective broadband wireless technologies are required to support the foreseeable need to process and exchange large amounts of data. In this Special Issue of the Springer Journal of Signal Processing Systems various disciplines of such efficiency and effectiveness in the context of Software-Defined Radio (SDR) technologies are discussed. At first, a selection of articles focuses on “spectral efficiency”. Since frequency spectrum is known to be scarce and limited, it becomes a resource of increasing value whose utilization must be handled with care. The rapidly growing demand for higher data throughputs in wireless communication does not allow inefficient use of spectrum anymore. Two promising approaches to tackle the “spectral efficiency” issue are Cognitive Radio (CR) and Dynamic Spectrum Access (DSA). A Cognitive Radio is capable of learning and adapting to its transmission environment. Taking e.g. spectrum sensing results into account, the decisions for accessing the scarce frequency spectrum in the most flexible and effective manner are made. CRs are typically based on SDR technology. Thus, the first set of articles puts emphasis on topics in the areas of Cognitive Radio, Cognitive Radio Networks, and Spectrum Sensing. The second selection of articles addresses the problems of “energy efficiency” and “implementation efficiency”. Especially in wireless communications these types of efficiencies are highly important to increase battery time of modern SDRbased platforms. The architectures of such SDRs are typically based on heterogeneous multi-processor hardware platforms hosting General Purpose Processors (GPP), Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) and sometimes even more specific processing elements. Each type of processor has a specific advantage in one or the other performance criterion like energy consumption, flexibility, processing time, throughput, waveform portability, components reusability etc. Whenever a new waveform shall be implemented on an SDR, the system designer has to take the decision for the best possible trade-off between all of these, partly conflicting, criteria under the given circumstances. For instance, the portability of waveform components can be improved by fulfilling the constraints of the Software Communications Architecture (SCA) specification and by using common Application Programming Interfaces (API). Thus, the second set of articles puts particular emphasis on topics in the areas of SDR and SCA Implementations.