Solderability of Surface Mount Devices

"Electronic manufacturing is currently one of the fastest growing industrial areas. This is due to the rapid advances in the computer and telecommunications sectors. Due to these advances, new surface mount devices have been developed to achieve greater miniaturisation at lower costs. As a result, a new surface mount technology has been developed to mount these devices onto printed circuit boards. However, problems exist with aspects of this process, principally open solder joints which result from circuit board warpage. The aim of this thesis is to undertake a) both an experimental and theoretical investigation of the reflow solder process and b) to develop thermal and structural models to analyse circuit board warpage. This research should aid manufacturing engineers in understanding the influence of the solder reflow process parameters on board warpage. Extensive experimental testing of the circuit board materials during the process is also presented. The thermal model detailed in this thesis simulates a) forced convective heat transfer through air impingement to the boards and b) the three dimensional temperature distribution within a composite laminate. The thermal model predicts the temperature distribution within a populated laminated composite circuit board to within 3% when compared to experimental data. The experimental results show that the convective heat transfer coefficient is primarily dependant on Reynolds number, and also the orifice to plate distance and orifice diameter. It was found that at high Reynolds number, the heat transfer coefficient increases significantly at low orifice to board distance. This heat transfer rate has to be balanced against the maximum speed of the air to prevent the components been blown off the boards. The 5mm diameter orifice provides the optimum balance between air speed and heat transfer rate. The structural model simulates the influence of a) board support, b) reflow temperature profile, c) components on the board and d) board layup on circuit board deformation. The experimental appraisal and model predictions show that the warpage of the printed circuit boards is dependant on a) support of the board during the process, b) symmetry of the board layup, c) coefficients of thermal expansion of the board materials, d) temperature distribution in the boards i.e. symmetric or nonsymmetric about board centre and e) temperature applied to the board. This research proves that if adequate support is applied to the boards during the reflow soldering process then, the warpage of the printed circuit boards may be kept within acceptable margins. Board warpage exists in current printed circuit boards because a) the boards cannot be manufactured truly symmetric in layup and b) Non-uniform temperature distributions are present in the board during the solder reflow process which leads to non-uniform expansion of the constituent laminate layers due to their varying coefficients of thermal expansion."

Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.

The surface mounting of electronic component is the major manufacturing technology for the electronic products in the last decade. The surface mounting technology (SMT) is an assembly process that assembles the surface mountable component (SMC) and the printed circuit board (PCB) together. The SMT mounter is an automatic assembly machine that processes the SMT assemblies in terms of the optical positioning and robotic handling. The SMT assembly consists of calibrating printed circuit board (PCB); vacuuming components form feeder stations; compensating the orientation of the vacuumed surface mountable component (SMC); and finally placing SMC chips on the PCB. In order to increase the throughput, the synchronous batch vacuuming of SMC components is designed. In addition, different types of component feeding and mixing in each batch increase the difficulties of finding the best component mounting sequence. In this paper, the optimal component placement scheduler is desired to perform higher assembly performance and to reduce the cycle time. The proposed optimal component placement scheduler is developed based on the rule based heuristic search approach. In addition, to evaluate the cycle time of each heuristic search, the route oriented Petri nets (ROPN) based SMT assembly models are constructed. The optimal component placement scheduler can be further determined in terms of evaluating the ROPN SMT assembly models. Finally, the practical test PCB board data is discussed in this paper.

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.

The most of the people using vehicles which have become the most important part in our life for transportation. In existing system the main snags are glaring effect accidents due to opposite vehicle headlight illumination at night driving. Second the short circuit fault in automotive wiring. Third is to perceive gas leakage fire accidents. Fourth faults due to increase in temperature on engine. Fifth higher sound in horn which cause disturbance in restricted surroundings. Sixth inaccurate fuel level monitoring in analog meter. Seventh accidents due to unequal wheel pressure. The proposed system has two modules Master and Slave they are communicating through CAN (Controller Area Network). The hardware has been developed in SMT (Surface Mount Technology) with SMD (Surface Mount Device) components and the hardware uses double layer PCB (Printed Circuit Board) design to optimize the space requirement and power consumption. The proposed system will be in cost effective safety system, reliability and hardware size will be small.

The rapid growth of modern technology place greater demand on electronic products’ performance and quality. As for the printed circuit board (PCB) assembly of electronic components through surface mounting technology (SMT), high-pixel charge coupled device (CCD) can only screen local images during image collection because of its limited vision. A rapid image mosaic technology has been proposed to seamlessly stitch the local images with overlapping boundaries. The complete image of PCB assembly has been acquired through rapid area matching method within double Mark points and Mark circle. The experiment results show that this method can greatly reduce the image-mosaic time and fairly improve the real-time performance of modern automatic optical inspection (AOI) equipment. Furthermore, such method avoids the alignment error from the characteristic points for noise jamming or noise shielding, and therefore obtains better robustness.

In surface mount technology, development toward green manufacturing by converting all leaded soldering processes to lead free soldering process has created a lot of challenges mainly in wave soldering process which led to copper dissolution to assemble board causing it to be scrapped if not contained. The paper aims to propose a workable and practical solution to reduce extensive copper dissolution in assemble board and expand the cycle of allowable rework in assemble board. The work was carried out using Six Sigma methodology with defining the problem and research goals, measure the details in various aspects of current process, analyse data to identify potential root cause in a process, improve the process and control the process through experimental approaches. Main factors contributing to copper dissolution were identified and analysed. Total of five factors were identified namely the printed circuit board (PCB) finishing and copper layer construction in PCB, component terminal and led finishing, soldering flux usage and solder alloy composition, environment control with the use of Nitrogen tunnelling and the last factor was on the process itself which was from the in-contact process with molten turbulence soldering or non-contact process with intrusive soldering. Combined controlled factors contributing to minimization of copper dissolution by reducing the direct contact time to molten solder with optimize solder alloy composition and process control was formulated. An increase of sixty percentage of boards with lower copper dissolution going through the lead free wave soldering and rework soldering were obtained, another forty percent reduction of board being scrapped were also obtained with boards going through the molten solder up to triple times.

The popularity of Ball Grid Array (BGA) has been gaining momentum in the past few years. From a board assemblers' perspective, BGA offers a wide process window and low process defect rate. In the early years, the reliability of the BGA solder joints was a concern because the BGA joints are non-compliant in comparison to the joints of gull-wing QFPs. Since then many finite element analysis (FEA) and reliability studies have been published demonstrating that BGA solder joints can have adequate reliability against the shear stress caused by the mismatch of coefficient of thermal expansion (CTE). Another mode of BGA joint failure, which has not been discussed as much, is the flexure-induced failure. In a typical electronics manufacturing environment, the printed circuit boards are handled many times after surface mount and wave soldering. Hand soldering, rework, in-circuit test, functional test, and final assembly are just some of the processes before the product is eventually shipped. Most of these processes can cause bending or warping of the printed circuit assembly (PCA), On a PCA, the areas under and adjacent to the BGA components are relatively rigid compared to the rest of the board. Hence, with the same amount of board flexing, the BGA solder joints become more susceptible to fracture compared to other surface mount devices. This study employed thermal cycling, dye-penetrant test, cross-sectioning, highly accelerated life test (HALT, thermal/vibration test), highly accelerated stress auditing (HASA, thermal/vibration test), “sticky probe” with in-circuit test (ICT) fixture and strain gage measurement to investigate the failure mechanism, and to determine the effects associated with board flexure. It was discovered that excessive flexing of PCA does cause catastrophic BGA solder joint cracking. Localized board flexure during in-circuit test was found to be very high and detrimental. BGA solder joints can crack during the in-circuit test and result in opens or intermittent failures. The ICT fixture should be carefully designed and manufactured to minimize local board warp around the BGA components. A FEA tool to analyze the localized strain on the PCA can be very helpful in ICT fixture design.

A profile identification system for surface mount printed circuit board assembly

The effect of anticoagulants, enzyme inhibitors and long term storage on the extraction of known concentrations of methionine enkephalin in human plasma

Tin-Bismuth (SnBi) solder alloys are being explored in the consumer electronics industry due to the benefit of low reflow temperatures when compared to Tin-Silver-Copper (SAC solders). These benefits include cost savings due to lower reflow temperatures in reflow ovens, reduction of temperature-driven component warpage, and elimination of the high-temperature material costs for components and printed circuit boards (PCB) to survive a SAC reflow process. An additional benefit of the SnBi’s low reflow temperature is the potential for eliminating the selective or wave soldering process and associated operating costs and factory space by soldering through-hole components with a Pin-in-Paste (PiP) process. The cost of a wave soldering tool can exceed $300,000 and switching to the PiP process can help eliminate this expense along with savings associated with tool maintenance, raw materials, and headcount. PiP uses a Surface Mount Technology (SMT) process to print solder paste at and around the Through Hole Mount (THM) location. Leads of the THM part can then be placed or inserted in the paste deposit either by an automated machine or manually. Paste forms a solder joint with the leads and via when the boards are sent through the reflow oven. Thus, this process can be combined with routine SMT parts and improve the throughput. Many papers have successfully demonstrated SAC PiP through hole soldering. However, the SAC PiP process has not gained traction due to the increased material costs for through-hole components that can survive SAC reflow temperatures which can be between 230ºC-250ºC. LTS solder paste reduces reflow temperatures to below 190ºC which makes it feasible for components with a lower temperature rating to be soldered during SMT reflow via Pin in Paste process. A drawback of the PiP process is that it can be difficult to achieve sufficient and uniform barrel fill as it involves the use of a stencil to print the necessary paste volume on the board. Stencil printing has an inherent limitation on the amount of paste volume it can deposit due to restrictions on the X, Y, and Z dimensions of the stencil aperture. This limitation is not observed at the wave and selective as they provide a continuous flow of solder paste to the PTH component to meet the higher paste volumes needed to fill the PTH barrel. This paper addresses various methods to overcome the limitations of the PiP process by defining the formula needed to calculate necessary solder paste volume. It recommends a ratio for the barrel to lead diameter, a comparison between the effect of board thickness on barrel fill percentage, and a proposal to use 100% lead coverage criteria for boards thicker than 62 mils. A lead pull test was performed on the 2x4 headers built with 100% lead coverage solder joint quality (SJQ) criteria using SnBi PiP process to study its solder joint strength and co-relate solder joint quality between the PiP and the Wave process. The test results were inconclusive in comparing SJQ between PiP and Wave as the pull test fixture failed to hold on to the header after 1kg of pulling force due to slippage.

FlashSoldering is a new innovative, non-contact, localized reflow soldering process initially developed for terminating fine insulated copper magnet wires to electronic contacts without first removing the wire insulation. Subsequent research has extended FlashSoldering applications to joining fine magnet wires to high-speed data connectors, joining flexible ribbon cables to rigid printed circuit boards (PCB), and reflow soldering miniature surface mount (SMT) components and connectors to flexible or rigid PCB's. Four elements comprise the FlashSoldering System. The first element is the substrate, which can be a flexible or rigid PCB. The second element is the SMT component or connector with “gull wing” style leads or a flexible ribbon cable. The third element is a precise amount of solder. The solder is plated onto both the substrate or component leads or is mechanically attached to the component or connector leads in the form of a solder bearing “nugget” which may contain flux. Solder can also be applied in the form of a precise amount of dispensed solder paste. The fourth and final element is a diode laser heat source. Non-contact diode laser heat reflows the solder plating or solder bearing “nugget” on the SMT component to the substrate to complete the solder joint. Applications for FlashSoldering include: single and multiple toroidal transformer packaging; LAN filters; low power DC-DC converters; woven or braided high speed data cables; and miniature temperature sensitive SMT components, connectors, and flexible ribbon cable attachment to rigid or flexible PCB's.

Early transistor and diode encapsulation was accomplished by dispensing a small amount of silicone or flexible epoxy over the die and bond wires in a process known as ‘glob-top’. However, the drive for low-cost, high-volume packaged semiconductor production soon initiated the introduction of transfer and injection moulding methods (see Chapter 5 for more details of transfer moulding materials and techniques). This move allowed polymeric encapsulants to replace the traditional but more expensive ceramic and metal packages in most areas except those requiring the highest reliability. The standard packaging format through the 1970s was the ubiquitous dual in-line plastic package and this really was the father of low-cost electronics packaging. The 1980s brought revolutionary changes in electronics technology in general, and in plastic packaging in particular. The main change from a packaging and assembly perspective was the move away from the use of through hole leaded components to the use of surface mount technology and the use of so-called surface mount devices (SMDs). These newer surface mount devices were both cheaper and easier to assemble than their predecessors and with leads on all four sides of the IC packages, surface mount technology initially offered opportunities for increased packaging density. This change to SMD, although not requiring any radically different package moulding techniques, did initiate a lot of work in the modification and optimization of moulding compounds for these generally much smaller packages. Unfortunately, it soon became apparent that conventional plastic quad leaded flat pack packages could not continue to accommodate the increasing numbers of leads required of future devices without either unacceptable increases in package area or moves to much finer pitches that would be difficult to handle and assemble. There has thus been major development of packaging techniques over the last few years, which in turn have necessitated the development of many new materials.

The investigation deals with soldering processes modeling in machines for surface mounting technologies (SMT) with new type of low inert heaters for the middle infrared spectral region. Its purpose is to be used for electronic control in soldering techniques for surface mounted devices (SMD). The approach to thermodynamic processes description is considered. The main parameters of heat transfer processes are analyzed. The proposed model describes heat transfer processes in soldering camera as a function of time and camera dimensions. The influence of the main parameters of heaters' operation and hot gas circulation in the camera on the temperature distribution upon the PCB (printed circuit boards) is investigated