Optimization of Component Placement Scheduling for SMT Assemblies

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.

Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.

This paper presents a novel adaptive sliding mode control based on nonlinear sliding surface with disturbance observer (ANSMC-DOB) for precision trajectory tracking control of a surface mount technology (SMT) assembly machine. A two-degree-of-freedom model with time-varying parameter uncertainties and disturbances is built to describe the first axial mode of the pick-place actuation axis of the machine. According to the principle of variable damping ratio coefficient which makes the system have a nonovershoot transient response and a short settling time in the second-order system, the nonlinear sliding surface is designed for the sliding mode control (SMC). Since the upper bound value of the disturbances is unknown, the adaptive gain estimation is applied to replace the switching gain in the SMC. In order to settle the problem of SMC unrobust to the mismatched parameter uncertainties and disturbances, the nonlinear disturbance observer is introduced to estimate the mismatched disturbances and form the novel controller of ANSMC-DOB. The stability of sliding surfaces and control laws are verified by the Lyapunov functions. The simulation research and comparative experiments are conducted to verify the improvement of positioning accuracy and robustness by the proposed ANSMC-DOB in the SMT assembly machine.

: As electronic products become much smaller, a limiting factor in the reduction of product size has been the size of electronic components which make up the product. The leads of the current electronic components are inserted onto a printed circuit board through holes. Due to the use of wire leads, it becomes more difficult to decrease the size of the components. A new method was created to mount components directly to the surface of the printed circuit board. This new technique is surface mount technology. A concern over the use of this is experienced by the military. Since the leads are not inserted through the board and crimped before soldering as conventional components are mounted, there is some regard as to whether the components can be mounted securely to the board. Due to the high forces that many munitions experience when dispensed, it is imperative that the electronic components be soldered to the circuits boards so they will not slip out of place or fall from the board. The military also requires many munitions to lie dormant in storage warehouses for up to 20 years. When the munition is needed, it must perform reliably. Little work has been done to study the effects of this long-term storage on these surface mount devices particularly the ability of different soldering techniques used to attach surface mount components to printed circuit boards to withstand damaging effects of long-term storage.... Surface mount technology, Solderability, Wave soldering, Reflow soldering, Conductive adhesive curing, Long-term storage, Accelerated age testing.

Automated Optical Inspection (AOI) systems are indispensable for ensuring the quality of electronic components in modern manufacturing. The Find Plane Algorithm stands out as a key element dedicated to verifying component presence in AOI inspection. The algorithm scrutinizes the height of each Surface Mount Technology (SMT) component, confirming their adherence to predefined tolerance ranges while flagging those that deviate significantly as potential defects during the inspection process. This is a common occurrence in SMT assembly after completing one side of a double-sided assembly. To combat the false call issue, the fine plane algorithm offers the flexibility to adjust tolerance limits, which is a critical feature in AOI inspection. This effort has been explored in the context of Mini-Dual Inline Memory Modules (MiniDIMM) and Dual Inline Memory Modules (DIMM) modules. This research presents a detailed analysis of the Find Plane Algorithm's application, emphasizing its role in reducing false calls and enhancing the overall effectiveness and dependability of the inspection process. The inferences derived from experimentation demonstrate the adaptability of the algorithm, allowing it to effectively address distinct LinkIDs, various component types, and tolerance limits. By strategically modifying these limits, substantial reductions in false calls are achieved, paralleled with improvements in yield, defect detection precision, and a reduction in the Defects Per Million Opportunities and Parts Per Million metrics. This algorithm enhance the AOI inspection program in terms of authenticity of the program as well as false call reduction during inspection of SMT manufacturing process.

This paper presents reliability of surface mount technology (SMT) packaging assemblies compared to decades old pin grid array (PGA) assembled with hand soldering that were subjected to extreme cold thermal cycles representative of high-reliability applications for deep-space missions. The advanced SMT packages included commercial–off-the-shelf (COTS) column grid array (CGA), leaded thin small outline (TSOP), leadless quad flat no-lead (QFN), and passive technologies. Tin-lead eutectic solders were used for soldering; they were either in paste form for assembling SMT packages or solid wire for hand soldering plated-through hole (PTH) for PGA ceramic packages. It is a general perception that the PTH technologies are an order of magnitude more robust in thermal cycle reliability than SMTs. However, this may not be true under extreme cold environmental conditions. Design for reliability (DfR) may requires compromising the stand-off height of PGA assembly and the thickness of printed circuit board (PCB) to achieve the desired long-term reliability. This paper presents the key parameters affecting the reliability of SMT package assemblies including TSOP, QFN, CGA, and PGA assemblies as well as associated test results under standard and extreme cold harsh thermal shock/cycle conditions. The standard thermal cycle conditions for high-reliability applications included were in the range of (−55°C to 100°C) and (−55°C to 125°C) whereas extreme cold cycles were harsh (−135°C to 70°C) and (−120°C to 85°C), or milder (−110°C to 20°C). Test results presented include non-destructive optical/SEM and X-ray images and daisy-chain resistances as well as destructive failure analyses performed by X-sectioning. Finally, key findings for various packaging technologies under extreme cold thermal cycles are presented.

Printed circuit board assembly (PCBA) is the major portion of manufacturing processes of electronic manufacturing services (EMS) industry, where surface mounting technology (SMT) has become the primary assembly method. Two series-connected SMT placement machines in a SMT assembly line are often the bottlenecks due to the unevenly distributed workloads. This paper studies the line balancing of the SMT assembly line focusing on the workload distribution between the two placement machines. A heuristic approach is proposed to reduce the workload difference of the two machines without increasing the total machine setup time. A software, which can be used as an effective automation tool for a company, is then developed based on the heuristic model. This will increase the quality of the service that the company provides to its customers.

In surface mount technology, development toward green manufacturing by converting all leaded soldering processes to lead free soldering process has created a lot of challenges mainly in wave soldering process which led to copper dissolution to assemble board causing it to be scrapped if not contained. The paper aims to propose a workable and practical solution to reduce extensive copper dissolution in assemble board and expand the cycle of allowable rework in assemble board. The work was carried out using Six Sigma methodology with defining the problem and research goals, measure the details in various aspects of current process, analyse data to identify potential root cause in a process, improve the process and control the process through experimental approaches. Main factors contributing to copper dissolution were identified and analysed. Total of five factors were identified namely the printed circuit board (PCB) finishing and copper layer construction in PCB, component terminal and led finishing, soldering flux usage and solder alloy composition, environment control with the use of Nitrogen tunnelling and the last factor was on the process itself which was from the in-contact process with molten turbulence soldering or non-contact process with intrusive soldering. Combined controlled factors contributing to minimization of copper dissolution by reducing the direct contact time to molten solder with optimize solder alloy composition and process control was formulated. An increase of sixty percentage of boards with lower copper dissolution going through the lead free wave soldering and rework soldering were obtained, another forty percent reduction of board being scrapped were also obtained with boards going through the molten solder up to triple times.

The rapid growth of modern technology place greater demand on electronic products’ performance and quality. As for the printed circuit board (PCB) assembly of electronic components through surface mounting technology (SMT), high-pixel charge coupled device (CCD) can only screen local images during image collection because of its limited vision. A rapid image mosaic technology has been proposed to seamlessly stitch the local images with overlapping boundaries. The complete image of PCB assembly has been acquired through rapid area matching method within double Mark points and Mark circle. The experiment results show that this method can greatly reduce the image-mosaic time and fairly improve the real-time performance of modern automatic optical inspection (AOI) equipment. Furthermore, such method avoids the alignment error from the characteristic points for noise jamming or noise shielding, and therefore obtains better robustness.

"Electronic manufacturing is currently one of the fastest growing industrial areas. This is due to the rapid advances in the computer and telecommunications sectors. Due to these advances, new surface mount devices have been developed to achieve greater miniaturisation at lower costs. As a result, a new surface mount technology has been developed to mount these devices onto printed circuit boards. However, problems exist with aspects of this process, principally open solder joints which result from circuit board warpage. The aim of this thesis is to undertake a) both an experimental and theoretical investigation of the reflow solder process and b) to develop thermal and structural models to analyse circuit board warpage. This research should aid manufacturing engineers in understanding the influence of the solder reflow process parameters on board warpage. Extensive experimental testing of the circuit board materials during the process is also presented. The thermal model detailed in this thesis simulates a) forced convective heat transfer through air impingement to the boards and b) the three dimensional temperature distribution within a composite laminate. The thermal model predicts the temperature distribution within a populated laminated composite circuit board to within 3% when compared to experimental data. The experimental results show that the convective heat transfer coefficient is primarily dependant on Reynolds number, and also the orifice to plate distance and orifice diameter. It was found that at high Reynolds number, the heat transfer coefficient increases significantly at low orifice to board distance. This heat transfer rate has to be balanced against the maximum speed of the air to prevent the components been blown off the boards. The 5mm diameter orifice provides the optimum balance between air speed and heat transfer rate. The structural model simulates the influence of a) board support, b) reflow temperature profile, c) components on the board and d) board layup on circuit board deformation. The experimental appraisal and model predictions show that the warpage of the printed circuit boards is dependant on a) support of the board during the process, b) symmetry of the board layup, c) coefficients of thermal expansion of the board materials, d) temperature distribution in the boards i.e. symmetric or nonsymmetric about board centre and e) temperature applied to the board. This research proves that if adequate support is applied to the boards during the reflow soldering process then, the warpage of the printed circuit boards may be kept within acceptable margins. Board warpage exists in current printed circuit boards because a) the boards cannot be manufactured truly symmetric in layup and b) Non-uniform temperature distributions are present in the board during the solder reflow process which leads to non-uniform expansion of the constituent laminate layers due to their varying coefficients of thermal expansion."

Multi-head gantry machines are becoming increasingly popular in surface mount technology (SMT), because they combine high printing speed with a moderate price. The optimization of their operation seems, however, to be very difficult. We formalize here a small subproblem of the scheduling problem of multi-headed SMT machines, namely the selection of nozzles which pick up and place components on printed circuit boards (PCB). The aim in this selection is to minimize the number of component pickups when manufacturing some PCB type. Given a sequence of component placement commands, a greedy nozzle usage policy picks, at each pickup, as many components next in the sequence as possible. If the nozzles are ‘universal’, that is, they can pick up any component, it is obvious that this policy is optimal. The situation gets more complicated once certain component types can be picked up only with certain nozzle types. We show that the greedy policy is optimal in this case, too. Finally, we do some experiments aimed at a better understanding of this subproblem.

The volume and complexity of printed circuit boards (PCBs) that use surface mount technology has increased tremendously over the past decade. The intricacy of the design and manufacturing functions associated with this domain is continuously increasing. Several researchers have documented the significance of the design functions on product life cycle costs. In the surface mount PCB assembly area, the integration of the design and manufacturing activity is hampered by the lack of sufficient, in-depth manufacturing knowledge among the PCB designers. Also, the heuristic nature of manufacturing knowledge coupled with the frequent advances in the state-of-the-art has resulted in the lack of widespread in-depth process knowledge.

A point-of-load power supply is designed for use in a distributed power system. In order to be commercially viable this supply requires low-cost components and packaging, while maintaining a small footprint and a half-inch height for interboard spacing requirements. The unique combination of direct-bond copper, surface mount, and advanced magnetic technologies permits an estimated maximum hybrid power density of 40 W/in/sup 3/ while using low-cost, readily available commercial components. Packaging details of a 100 W prototype operating at 1 MHz with 34 W/in/sup 3/ hybrid power density are described, including packaging constraints caused by the electrical requirements of the resonant topology utilized. In addition, thermal considerations which must be met in order to reach the maximum hybrid power density are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Tin-Bismuth (SnBi) solder alloys are being explored in the consumer electronics industry due to the benefit of low reflow temperatures when compared to Tin-Silver-Copper (SAC solders). These benefits include cost savings due to lower reflow temperatures in reflow ovens, reduction of temperature-driven component warpage, and elimination of the high-temperature material costs for components and printed circuit boards (PCB) to survive a SAC reflow process. An additional benefit of the SnBi’s low reflow temperature is the potential for eliminating the selective or wave soldering process and associated operating costs and factory space by soldering through-hole components with a Pin-in-Paste (PiP) process. The cost of a wave soldering tool can exceed $300,000 and switching to the PiP process can help eliminate this expense along with savings associated with tool maintenance, raw materials, and headcount. PiP uses a Surface Mount Technology (SMT) process to print solder paste at and around the Through Hole Mount (THM) location. Leads of the THM part can then be placed or inserted in the paste deposit either by an automated machine or manually. Paste forms a solder joint with the leads and via when the boards are sent through the reflow oven. Thus, this process can be combined with routine SMT parts and improve the throughput. Many papers have successfully demonstrated SAC PiP through hole soldering. However, the SAC PiP process has not gained traction due to the increased material costs for through-hole components that can survive SAC reflow temperatures which can be between 230ºC-250ºC. LTS solder paste reduces reflow temperatures to below 190ºC which makes it feasible for components with a lower temperature rating to be soldered during SMT reflow via Pin in Paste process. A drawback of the PiP process is that it can be difficult to achieve sufficient and uniform barrel fill as it involves the use of a stencil to print the necessary paste volume on the board. Stencil printing has an inherent limitation on the amount of paste volume it can deposit due to restrictions on the X, Y, and Z dimensions of the stencil aperture. This limitation is not observed at the wave and selective as they provide a continuous flow of solder paste to the PTH component to meet the higher paste volumes needed to fill the PTH barrel. This paper addresses various methods to overcome the limitations of the PiP process by defining the formula needed to calculate necessary solder paste volume. It recommends a ratio for the barrel to lead diameter, a comparison between the effect of board thickness on barrel fill percentage, and a proposal to use 100% lead coverage criteria for boards thicker than 62 mils. A lead pull test was performed on the 2x4 headers built with 100% lead coverage solder joint quality (SJQ) criteria using SnBi PiP process to study its solder joint strength and co-relate solder joint quality between the PiP and the Wave process. The test results were inconclusive in comparing SJQ between PiP and Wave as the pull test fixture failed to hold on to the header after 1kg of pulling force due to slippage.