A knowledge-based object oriented DFM advisor for surface mount PCB assembly

The surface mounting of electronic component is the major manufacturing technology for the electronic products in the last decade. The surface mounting technology (SMT) is an assembly process that assembles the surface mountable component (SMC) and the printed circuit board (PCB) together. The SMT mounter is an automatic assembly machine that processes the SMT assemblies in terms of the optical positioning and robotic handling. The SMT assembly consists of calibrating printed circuit board (PCB); vacuuming components form feeder stations; compensating the orientation of the vacuumed surface mountable component (SMC); and finally placing SMC chips on the PCB. In order to increase the throughput, the synchronous batch vacuuming of SMC components is designed. In addition, different types of component feeding and mixing in each batch increase the difficulties of finding the best component mounting sequence. In this paper, the optimal component placement scheduler is desired to perform higher assembly performance and to reduce the cycle time. The proposed optimal component placement scheduler is developed based on the rule based heuristic search approach. In addition, to evaluate the cycle time of each heuristic search, the route oriented Petri nets (ROPN) based SMT assembly models are constructed. The optimal component placement scheduler can be further determined in terms of evaluating the ROPN SMT assembly models. Finally, the practical test PCB board data is discussed in this paper.

Surface mount technology (SMT) is being increasingly used in printed circuit board (PCB) assembly. The reduced lead pitch of surface mount components coupled with their increased lead count and packing densities have made it imperative that automated placement methods be used. However, the SMT placement process is often a bottleneck in surface mount manufacturing. A reduction in placement time in SMT will enhance throughput and productivity. This paper describes the design and development of a prototype expert system based approach which identifies ‘near’ optimal placement sequences for surface mount PCBs in (almost) realtime. The software structure used integrates a knowledge based system with an optimisation module. PROLOG is the language used in this research. The system was rigorously validated and tested. Ideas for further research are also presented.

Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.

: As electronic products become much smaller, a limiting factor in the reduction of product size has been the size of electronic components which make up the product. The leads of the current electronic components are inserted onto a printed circuit board through holes. Due to the use of wire leads, it becomes more difficult to decrease the size of the components. A new method was created to mount components directly to the surface of the printed circuit board. This new technique is surface mount technology. A concern over the use of this is experienced by the military. Since the leads are not inserted through the board and crimped before soldering as conventional components are mounted, there is some regard as to whether the components can be mounted securely to the board. Due to the high forces that many munitions experience when dispensed, it is imperative that the electronic components be soldered to the circuits boards so they will not slip out of place or fall from the board. The military also requires many munitions to lie dormant in storage warehouses for up to 20 years. When the munition is needed, it must perform reliably. Little work has been done to study the effects of this long-term storage on these surface mount devices particularly the ability of different soldering techniques used to attach surface mount components to printed circuit boards to withstand damaging effects of long-term storage.... Surface mount technology, Solderability, Wave soldering, Reflow soldering, Conductive adhesive curing, Long-term storage, Accelerated age testing.

The most of the people using vehicles which have become the most important part in our life for transportation. In existing system the main snags are glaring effect accidents due to opposite vehicle headlight illumination at night driving. Second the short circuit fault in automotive wiring. Third is to perceive gas leakage fire accidents. Fourth faults due to increase in temperature on engine. Fifth higher sound in horn which cause disturbance in restricted surroundings. Sixth inaccurate fuel level monitoring in analog meter. Seventh accidents due to unequal wheel pressure. The proposed system has two modules Master and Slave they are communicating through CAN (Controller Area Network). The hardware has been developed in SMT (Surface Mount Technology) with SMD (Surface Mount Device) components and the hardware uses double layer PCB (Printed Circuit Board) design to optimize the space requirement and power consumption. The proposed system will be in cost effective safety system, reliability and hardware size will be small.

Printed circuit boards (PCBs) are the essential parts to assemble modern electronic circuits. The PCB design and development process has a direct impact on the system cost and time to market. On average, companies report that PCB represents 31% of the overall product cost. Today's electronic circuits and PCB designs are extremely complex. Multi-level mistakes are inevitable during the design and development stages. Cost reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs. A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity, shortens design to market time, and simplifies the overall supply chain. In order to develop a superior product to fulfill a desired functions, good balance needs to be achieved among competing factors such as performance, cost, form factors, manufacturability, design, system flexibility, and supply chain management (Fig 1). A wireless system is usually comprised of several subsystems performing different functions. For example, a typical handset system includes baseband, transceivers, main and diversity FEM, memories, power management, power amplifiers, antenna switch, duplexer filter, etc. In this day and age, system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution, system level integration at the packaging level may provide benefits such as cost effectiveness, flexibility, and a shorter development cycle. A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package.

In order to improve the design of products and reduce design changes, cost, and time to market, life cycle engineering has emerged as an effective approach to address these issues in today's competitive global market. As over 70% of the total life cycle cost of a product is committed at the early design stage, designers can substantially reduce the life cycle cost of products by giving due consideration to the life cycle implications of their design decisions. During the early design stages there may be competing requirements. In addition, detailed information is scarce and decisions must be made quickly. Thus, both the overhead in developing parametric life cycle cost (LCC) models for a wide range of concepts or requirements, and the lack of detailed information make the application of traditional LCC models impractical. A different approach is required because a traditional LCC method should be incorporated in the very early design stages. This paper explores an approximate method for providing the preliminary life cycle cost. Learning algorithms trained to use the known characteristics of existing products can perhaps allow the life cycle cost of new products to be approximated quickly during the conceptual design phase without the overhead of defining new LCC models. Artificial neural networks are trained to generalise product attributes and life cycle cost data from pre-existing LCC studies. Then, the product designers query the trained artificial model with new high-level product attribute data to obtain an LCC for a new product concept quickly. Foundations for the learning LCC approach are established, and then an application is provided. This paper has been developed to provide designers with LCC information to guide them in conceptual design.

For the same blocking voltage rating and on-state resistance, Silicon Carbide (SiC) MOSFETs die is thinner and smaller compared to Si counterpart due to SiC material's superior electric-field withstanding capability. This smaller die size improves the switching performance significantly but deteriorates the thermal performance of the device packaging. This makes thermal design more challenging when using SiC MOSFETs. When using surface-mount (SM) packaging, printed circuit board (PCB) design plays a key role in the overall thermal design. Understanding the PCB design choices is necessary to maximize the performance of SM SiC MOSFET. This paper investigates several key factors in the thermal design of FR4 PCB to reduce junction temperature (Tj) of surface-mount (SM) SiC MOSFETs in steady-state and overload transient conditions. The factors of interest include heat sinks, copper area per device, and copper thickness. In experiments, doubling PCB copper area can reduce Δ <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T_{j}$</tex> by > 40% in steady-state operation, making it the dominant factor. Experiments are performed on a two-layer PCB with a 900 V, 20 mΩ SiC device in D2Pak-7L package. For steady-state performance, doubling PCB copper area reduced the junction temperature rise by > 40%, making it the dominant design factor for steady-state thermal performance. For transient tests, copper thickness is the most critical factor. Junction temperature rise reduced by > 30% when PCB copper thickness is increased from 2 ounces (oz) to 6 oz. Experimental data is provided at various current stress levels for nominal steady-state and overload transient conditions. The findings provide thermal design guidelines of FR4 PCB for SM SiC MOSFETs in various applications.

Printed Circuit Boards (PCBs) are widely used in most electronic devices. Typically, a PCB design has a set of components that needs to be assembled. In a broad sense, this assembly task involves placing PCB components at designated location on a PCB board; fixing PCB components; and testing the PCB after assembly operation to ensure that it is in proper working order. The stringent requirements of having a higher component density on PCBs, a shorter assembly time, and a more reliable product prompt manufacturers to automate the process of PCB assembly. Frequently, a few placement machines may work together to form an assembly line. Thus, the application of more than one machine for component placement on a PCB presents a line-balancing problem, which is basically concerned with balancing the workload of all the machines in an assembly line. This paper describes the application of a new artificial intelligence technique known as the immune algorithm to PCB component placement as well as the line balancing of PCB assembly line. It also includes an overview of PCB assembly and an outline of the assembly line balancing problem. Two case studies are used to validate the IA engine developed in this work. The details of IA, the IA engine and the case studies are presented.

Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.

A profile identification system for surface mount printed circuit board assembly

Process planning output can be post-processed into criteria for job scheduling decisions in printed circuit board assembly using surface-mount technology (SMT). Artificial intelligence-based techniques used in computerized planning and scheduling systems in other industries can be extended to printed circuit board operations. These techniques include blackboard architectures, object-oriented programming systems, and nonmonotonic reasoning systems. These techniques were used to demonstrate a unique architecture of blackboard systems that communicate via object-oriented messages to arrive at a shop-floor process plan and production schedule. The methodology was specialized to the assembly of printed circuit boards using surface-mounted components in a high-variety/low-volume product mix. The assembly facility was represented as a hierarchical object of product, process, and organizational knowledge. The system of working heuristics was integrated within a prototype environment with the practitioners that assisted in its development. The end result is a good working methodology for system development, implementation, and maintenance by knowledge worker involvement.

"Electronic manufacturing is currently one of the fastest growing industrial areas. This is due to the rapid advances in the computer and telecommunications sectors. Due to these advances, new surface mount devices have been developed to achieve greater miniaturisation at lower costs. As a result, a new surface mount technology has been developed to mount these devices onto printed circuit boards. However, problems exist with aspects of this process, principally open solder joints which result from circuit board warpage. The aim of this thesis is to undertake a) both an experimental and theoretical investigation of the reflow solder process and b) to develop thermal and structural models to analyse circuit board warpage. This research should aid manufacturing engineers in understanding the influence of the solder reflow process parameters on board warpage. Extensive experimental testing of the circuit board materials during the process is also presented. The thermal model detailed in this thesis simulates a) forced convective heat transfer through air impingement to the boards and b) the three dimensional temperature distribution within a composite laminate. The thermal model predicts the temperature distribution within a populated laminated composite circuit board to within 3% when compared to experimental data. The experimental results show that the convective heat transfer coefficient is primarily dependant on Reynolds number, and also the orifice to plate distance and orifice diameter. It was found that at high Reynolds number, the heat transfer coefficient increases significantly at low orifice to board distance. This heat transfer rate has to be balanced against the maximum speed of the air to prevent the components been blown off the boards. The 5mm diameter orifice provides the optimum balance between air speed and heat transfer rate. The structural model simulates the influence of a) board support, b) reflow temperature profile, c) components on the board and d) board layup on circuit board deformation. The experimental appraisal and model predictions show that the warpage of the printed circuit boards is dependant on a) support of the board during the process, b) symmetry of the board layup, c) coefficients of thermal expansion of the board materials, d) temperature distribution in the boards i.e. symmetric or nonsymmetric about board centre and e) temperature applied to the board. This research proves that if adequate support is applied to the boards during the reflow soldering process then, the warpage of the printed circuit boards may be kept within acceptable margins. Board warpage exists in current printed circuit boards because a) the boards cannot be manufactured truly symmetric in layup and b) Non-uniform temperature distributions are present in the board during the solder reflow process which leads to non-uniform expansion of the constituent laminate layers due to their varying coefficients of thermal expansion."

Channel loss is a dominant factor for the signaling performance of high-speed I/O's. Some platform design guides clearly specify the printed-circuit board (PCB) loss requirement. During the initial design stage for PCB material selection, platform designers would like to have the accurate and efficient insertion loss measurement to meet the channel requirement because the PCB material contributes largely to the platform cost. In this paper, a comprehensive study on PCB design and analysis by different industrial methodologies for insertion loss characterization was conducted. Delta-L 2.0 methodology result is correlated with 2x-Thru results and it is good to utilize this for PCB electrical characterization. The de-embedding structure by 4 inch and 2 inch with handheld probes is validated in the accuracy, efficiency and compact test coupon size, compared with the design with 10 inch and 5 inch by SMA.

This paper presents reliability of surface mount technology (SMT) packaging assemblies compared to decades old pin grid array (PGA) assembled with hand soldering that were subjected to extreme cold thermal cycles representative of high-reliability applications for deep-space missions. The advanced SMT packages included commercial–off-the-shelf (COTS) column grid array (CGA), leaded thin small outline (TSOP), leadless quad flat no-lead (QFN), and passive technologies. Tin-lead eutectic solders were used for soldering; they were either in paste form for assembling SMT packages or solid wire for hand soldering plated-through hole (PTH) for PGA ceramic packages. It is a general perception that the PTH technologies are an order of magnitude more robust in thermal cycle reliability than SMTs. However, this may not be true under extreme cold environmental conditions. Design for reliability (DfR) may requires compromising the stand-off height of PGA assembly and the thickness of printed circuit board (PCB) to achieve the desired long-term reliability. This paper presents the key parameters affecting the reliability of SMT package assemblies including TSOP, QFN, CGA, and PGA assemblies as well as associated test results under standard and extreme cold harsh thermal shock/cycle conditions. The standard thermal cycle conditions for high-reliability applications included were in the range of (−55°C to 100°C) and (−55°C to 125°C) whereas extreme cold cycles were harsh (−135°C to 70°C) and (−120°C to 85°C), or milder (−110°C to 20°C). Test results presented include non-destructive optical/SEM and X-ray images and daisy-chain resistances as well as destructive failure analyses performed by X-sectioning. Finally, key findings for various packaging technologies under extreme cold thermal cycles are presented.