SOML Read

A large write amplification ratio degrades the program/erase cycles (P/Es) of NAND Flashes and reduces the endurance and performance of solid state disks (SSDs). The lack of a practical way to measure write amplification for SSDs motivates us to propose a novel measuring method called RB-Explorer at the SSD level rather than the NAND Flash level. The goal of RB-Explorer is two-fold: (1) to accurately measure the write amplification of SSDs to quantify SSD endurance and (2) to study the impacts of I/O techniques on write amplification of SSDs. RB-Explorer incorporates a Ready/Busy (R/B) signal of one of the NAND Flashes in an SSD in a proposed write amplification model for SSDs with four full-parallelism levels (i.e., the channel, chip, die, and plane levels). RB-Explorer takes two steps toward measuring write amplification. First, RB-Explorer quantifies the number of page programs using the low R/B signal level, the duration of which varies with the different operation (i.e., read, program, and erase) in NAND Flash. Second, RB-Explorer measures data volume written to NAND Flashes by considering parallelisms at four levels. Data volume written to a die in a NAND Flash is obtained as a product of the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> ${\rm N_{p}}$</tex><mathgraphic fileref="sun-ieq1-2308207.gif" graphicformat="GIF"/></formula> of programs and page size <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm P_{a}}$</tex> <mathgraphic fileref="sun-ieq2-2308207.gif" graphicformat="GIF"/></formula> . Given the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq3-2308207.gif" graphicformat="GIF"/></formula> of channels, the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{chip}}$</tex> <mathgraphic fileref="sun-ieq4-2308207.gif" graphicformat="GIF"/></formula> of chips per channel, and the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{die}}$</tex> <mathgraphic fileref="sun-ieq5-2308207.gif" graphicformat="GIF"/></formula> of dies per chip, one can obtain the data volume written to NAND Flashes as a product of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{p}}, {\rm P_{a}}, {\rm N_{die}}, {\rm N_{chip}}$</tex><mathgraphic fileref="sun-ieq6-2308207.gif" graphicformat="GIF"/></formula> , and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq7-2308207.gif" graphicformat="GIF"/></formula> . RB-Explorer is applied to analyzing write amplification ratios of SSDs to track SSD endurance. Furthermore, we implement a real-world SSD (i.e., SSD-v) and employ a fine-tuned SSD simulator (i.e., SSDsim) to validate the accuracy of RB-Explorer. Our experimental results show that RB-Explorer improves on the accuracy of SSDsim—the state-of-the-art SSD simulator—in most tested cases. We conduct a series of measurements using micro-benchmarks and I/O traces to demonstrate how RB-Explorer may be applied to investigate SSDs.

Solid State Disks (SSDs) are becoming increasingly popular due to enhancement in speed and reduction in size, power and cost. It is an obvious choice for many applications including personal computers, embedded systems, medical and healthcare devices etc. However, the reliability of SSD has now become a critical issue and this is an area of active research. SSD uses Flash technology which is a fast, efficient nonvolatile storage chip and offers cost-effective solution for SSDs. However, with all these features, flash memory defines a limit of write-erase on its blocks. Wearleveling policies extend SSD life time by ensuring even wearleveling of the blocks in a flash memory. Several algorithms have been proposed to improve wearleveling of SSD including Hot-Cold Swapping, Dual pool Algorithm (DP), Kim and Lee algorithm (KL) and Cost Age and Times Algorithm (CAT). This paper discusses all these wearleveling policies and introduces a Block Aging Prevention (BAP) technique which has been tested on 8Gb Flash. The comparison of all these algorithms show that the proposed technique has reduced the erasure count deviation of NAND flash blocks by 6.71% and 20% compared to DP and CAT respectively. It has also reduced overhead by 4% comparatively to DP.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Various key-value (KV) stores are widely employed for data management to support Internet services as they offer higher efficiency, scalability, and availability than relational database systems. The log-structured merge tree (LSM-tree) based KV stores have attracted growing attention because they can eliminate random writes and maintain acceptable read performance. Recently, as the price per unit capacity of NAND flash decreases, solid state disks (SSDs) have been extensively adopted in enterprise-scale data centers to provide high I/O bandwidth and low access latency. However, it is inefficient to naively combine LSM-tree-based KV stores with SSDs, as the high parallelism enabled within the SSD cannot be fully exploited. Current LSM-tree-based KV stores are designed without assuming SSD's multi-channel architecture.To address this inadequacy, we propose LOCS, a system equipped with a customized SSD design, which exposes its internal flash channels to applications, to work with the LSM-tree-based KV store, specifically LevelDB in this work. We extend LevelDB to explicitly leverage the multiple channels of an SSD to exploit its abundant parallelism. In addition, we optimize scheduling and dispatching polices for concurrent I/O requests to further improve the efficiency of data access. Compared with the scenario where a stock LevelDB runs on a conventional SSD, the throughput of storage system can be improved by more than 4X after applying all proposed optimization techniques.

In this paper, we propose a fast and simple system emulator, called a system performance emulator (SPE), to evaluate long read operations. The SPE estimates how much system-wide performance is enhanced by using a faster solid state disk (SSD). By suspending a CPU for a certain time during direct memory access (DMA) transfer and subtracting this suspended time from the total DMA time, the SPE estimates the improvement in system performance expected from an enhanced SSD prior to its manufacture. We also examine the relation between storage performance and system performance using the SPE.

Flash memory is now widely used in the design of solid-state disks (SSDs) as they are able to sustain significantly higher I/O rates than even high-performance hard disks, while using significantly less power. These characteristics make SSDs especially attractive for use in enterprise storage systems, and it is predicted that the use of SSDs will save 58,000 MWh/year by 2013. However, Flash-based SSDs are unable to reach peak performance on common enterprise data patterns such as log-file and metadata updates due to slow write speeds (an order-of-magnitude slower than reads) and the inability to do in-place updates. In this paper, we utilize an auxiliary, byte-addressable, non-volatile memory to design a general purpose merge cache that significantly improves write performance. We also utilize simple read policies that further improve the performance of the SSD without adding significant overhead. Together, these policies reduce the average response time by more than 75%, making it possible to meet performance requirements with fewer drives.

Solid state disks (SSDs) consisting of NAND flash memory are replacing conventional HDDs in mobile and server markets. The major reason for such a widespread replacement is the high performance and low power consumption enabled by an SSD. It especially gives better performance and power efficiency for random requests, because it does not require slow-moving and power-hungry mechanical operations, e.g., motor control. For the performance of sequential requests, multi-channel/way parallel architectures are adopted, and the speed of the host interface is increased. Even though an SSD has better power efficiency than an HDD, the SSD power consumption must be minimized due to the stringent power consumption constraints of mobile and server products. This chapter presents a case study of developing an SSD power model with an application to low power SSD design. The power model is based on real measurement data. For accurate modeling, one must take into account the internal parallelism as well as power states. The case study shows that the power model is useful in evaluating the designs of dynamic power management policy.

This letter presents a virtual platform of solid-state disks (SSDs). Using a set of programming interfaces, users can quickly assemble an SSD based on their preferred flash chip organization and flash management algorithm, and a virtual disk then appears in the host system as a logical instance of the SSD. Unlike previous SSD simulation tools, this virtual disk performs block read/write with realistic I/O latencies as if this simulated SSD was real. This virtual platform provides a swift way to SSD hardware and firmware prototyping, and it is also useful for future research on the paradigm of host-device interaction.

Flash memory is being actively employed in a variety of embedded systems such as digital cameras, MP3 players, cell phones, solid state disks (SSDs), and digital media broadcasting (DMB) devices. This paper considers performance issues in file systems that employ Flash memory as a storage medium. Firstly, it explores the characteristics of Flash memory and identifies the cost of block cleaning as the key performance bottleneck for Flash memory analogous to the seek time in disk storage. Then, it defines three performance parameters, namely, utilization, invalidity, and uniformity and derives a formula for block cleaning cost based on these parameters. It is shown that, of these parameters, uniformity exerts the strongest influence on the cost of cleaning and that uniformity is a file system controllable parameter. Finally, we design a uniformity-aware page allocation scheme and analyze how enhanced uniformity affects the block cleaning cost with various workloads. Real implementation experiments conducted on an embedded system show that the scheme proposed here typically reduces the cleaning time by 20 to 30% compared to the traditional sequential allocation scheme that is used in YAFFS.

In this paper, a partial parity cache and data cache management method is presented for reducing the parity updating cost of a solid-state disk (SSD) based redundant array of inexpensive disk (RAID) system, thereby which the input/output (I/O) performance of the RAID system can be improved. SSDs have many advantages compared to hard disk drives. However, it is not advisable to directly add SSDs into a RAID system because doing so will decrease the performance and the life-time of the SSDs. In the RAID-5 system, parity generation includes read and write operations to the SSDs. Whenever there is a new write request to the RAID, the related parity must be updated and written to the SSDs. Such frequent parity updates result in poor RAID performance and shortens the life-time of the SSDs. This paper combines the prior methods and the proposed efficient buffer management method with a data cache. The proposed method reduces the number of read and write operations for generating parities in the RAID system. Experimental results show that the I/O performance of the RAID-5 system can be improved by 76% by using the proposed method.

The internal copy (IC) is a simple, yet powerful in-storage processing function, which changes the locations of data blocks without invoking any data transfer between the host and storage. Owing to the out-of-place update constraint of flash memory, solid-state disks (SSDs) employ a flash translation layer (FTL) to manage the logical-to-physical address translation. By leveraging the address indirection feature of SSDs, the IC can be processed only by remapping flash pages to new logical addresses without flash read/write operations. In the existing studies on remap-based IC, SSDs were assumed to have only a single FTL instance. However, recent large-capacity SSDs adopt an arrayed architecture including multiple FTL controllers, where each controller runs an FTL instance to manage its own partitioned address space. For the arrayed SSDs, inter-partition copy requests cannot be handled by address remapping because each partition is managed by a different FTL instance. In this study, we propose an inter-partition remap technique for IC-enabled arrayed SSDs. Additionally, we present the block allocation technique to minimize the number of inter-partition copy requests. Our proposed IC techniques were implemented on an actual arrayed SSD, and showed significant performance improvements compared to the previous remap techniques in several use cases.

This paper explores the benefits and limitations of in-storage processing on current Solid-State Disk (SSD) architectures. While disk-based in-storage processing has not been widely adopted, due to the characteristics of hard disks, modern SSDs provide high performance on concurrent random writes, and have powerful processors, memory, and multiple I/O channels to flash memory, enabling in-storage processing with almost no hardware changes. In addition, offloading I/O tasks allows a host system to fully utilize devices' internal parallelism without knowing the details of their hardware configurations. To leverage the enhanced data processing capabilities of modern SSDs, we introduce the Smart SSD model, which pairs in-device processing with a powerful host system capable of handling data-oriented tasks without modifying operating system code. By isolating the data traffic within the device, this model promises low energy consumption, high parallelism, low host memory footprint and better performance. To demonstrate these capabilities, we constructed a prototype implementing this model on a real SATA-based SSD. Our system uses an object-based protocol for low-level communication with the host, and extends the Hadoop MapReduce framework to support a Smart SSD. Our experiments show that total energy consumption is reduced by 50% due to the low-power processing inside a Smart SSD. Moreover, a system with a Smart SSD can outperform host-side processing by a factor of two or three by efficiently utilizing internal parallelism when applications have light trafic to the device DRAM under the current architecture.

ZTL: A block layer ZNS driver

High performance and energy-efficient storage systems are essential for mobile data-intensive applications such as remote surgery and mobile data center. Existing mobile storage systems consist of an array of independent small form factor hard disks connected to a host by a storage interface in a mobile computing environment. Although hard disks are cost-effective and can provide huge capacity and high-throughput, they have some intrinsic limitations such as long access latencies, high annual disk replacement rates, fragile physical characteristics, and energy-inefficiency. Compared with hard disk drives, solid state disks (SSD) are much more energy-efficient, and can offer much faster access times. A major concern on current solid state disk is its relatively higher price. In this paper, we developed hybrid mobile disk architecture HyBuM that integrates an array of solid state disks with buffer disks and an array of mobile disks. The most recently used data will be cached in the solid state disks, the second most popular data will be stored in the buffer disks, and the least used data sets will be stored in the mobile disk array. Experimental results demonstratively show that HyBuM provides significant energy saving for mobile storage systems such as laptops, mobile phones, and PDA compared to two existing non hybrid architecture.

Recent advances in flash memory technology have reduced the cost-per-bit of flash storage devices such as solid-state drives (SSDs), thereby enabling the development of large-capacity SSDs for enterprise-scale storage. However, two major concerns arise in designing SSDs. First, the size of the address mapping table is increasing in proportion to the capacity of the SSD. The SSD-internal firmware, called flash translation layer (FTL), must maintain the address mapping table in the internal DRAM. Although the previously proposed demand map loading technique uses a small size of cached map table, the technique aggravates poor random performance. Second, there are many redundant writes in storage workloads, which have an adverse effect on the performance and lifetime of the SSD. For example, many transaction-supporting applications use the write-ahead-log (WAL) scheme, which writes the same data twice. To resolve these problems, we propose a novel transaction-supporting SSD, called WAL-SSD, which logs transaction data at the internally-managed WAL area and relocates the data atomically via the FTL-level remap operation at the transaction checkpointing. It can also be used to transform random write requests to sequential requests. We implemented a prototype of WAL-SSD with a real SSD device. Experiments demonstrate the performance improvement by WAL-SSD with three use cases: remap-journaling, atomic multi-block update, and random write logging.