A fast and simple system performance emulator for enhanced solid state disks: a case study of long read operations

NAND-based solid-state disks (SSDs) are known for their superior random read/write performance due to the high degrees of multi-chip parallelism they exhibit. Currently, as the chip density increases dramatically, fewer 3D NAND chips are needed to build an SSD compared to the previous generation chips. As a result, SSDs can be made more compact. However, this decrease in the number of chips also results in reduced overall throughput, and prevents 3D NAND high density SSDs from being widely-adopted. We analyzed 600 storage workloads, and our analysis revealed that the small read operations suffer significant performance degradation due to reduced chip-level parallelism in newer 3D NAND SSDs. The main question is whether some of the inter-chip parallelism lost in these new SSDs (due to the reduced chip count) can be won back by enhancing intra-chip parallelism. Motivated by this question, we propose a novel SOML (Single-Operation-Multiple-Location) read operation, which can perform several small intra-chip read operations to different locations simultaneously, so that multiple requests can be serviced in parallel, thereby mitigating the parallelism-related bottlenecks. A corresponding SOML read scheduling algorithm is also proposed to fully utilize the SOML read. Our experimental results with various storage workloads indicate that, the SOML read-based SSD with 8 chips can outperform the baseline SSD with 16 chips.

A large write amplification ratio degrades the program/erase cycles (P/Es) of NAND Flashes and reduces the endurance and performance of solid state disks (SSDs). The lack of a practical way to measure write amplification for SSDs motivates us to propose a novel measuring method called RB-Explorer at the SSD level rather than the NAND Flash level. The goal of RB-Explorer is two-fold: (1) to accurately measure the write amplification of SSDs to quantify SSD endurance and (2) to study the impacts of I/O techniques on write amplification of SSDs. RB-Explorer incorporates a Ready/Busy (R/B) signal of one of the NAND Flashes in an SSD in a proposed write amplification model for SSDs with four full-parallelism levels (i.e., the channel, chip, die, and plane levels). RB-Explorer takes two steps toward measuring write amplification. First, RB-Explorer quantifies the number of page programs using the low R/B signal level, the duration of which varies with the different operation (i.e., read, program, and erase) in NAND Flash. Second, RB-Explorer measures data volume written to NAND Flashes by considering parallelisms at four levels. Data volume written to a die in a NAND Flash is obtained as a product of the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> ${\rm N_{p}}$</tex><mathgraphic fileref="sun-ieq1-2308207.gif" graphicformat="GIF"/></formula> of programs and page size <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm P_{a}}$</tex> <mathgraphic fileref="sun-ieq2-2308207.gif" graphicformat="GIF"/></formula> . Given the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq3-2308207.gif" graphicformat="GIF"/></formula> of channels, the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{chip}}$</tex> <mathgraphic fileref="sun-ieq4-2308207.gif" graphicformat="GIF"/></formula> of chips per channel, and the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{die}}$</tex> <mathgraphic fileref="sun-ieq5-2308207.gif" graphicformat="GIF"/></formula> of dies per chip, one can obtain the data volume written to NAND Flashes as a product of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{p}}, {\rm P_{a}}, {\rm N_{die}}, {\rm N_{chip}}$</tex><mathgraphic fileref="sun-ieq6-2308207.gif" graphicformat="GIF"/></formula> , and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq7-2308207.gif" graphicformat="GIF"/></formula> . RB-Explorer is applied to analyzing write amplification ratios of SSDs to track SSD endurance. Furthermore, we implement a real-world SSD (i.e., SSD-v) and employ a fine-tuned SSD simulator (i.e., SSDsim) to validate the accuracy of RB-Explorer. Our experimental results show that RB-Explorer improves on the accuracy of SSDsim—the state-of-the-art SSD simulator—in most tested cases. We conduct a series of measurements using micro-benchmarks and I/O traces to demonstrate how RB-Explorer may be applied to investigate SSDs.

Multi-tiered storage systems today are integrating Solid State Disks (SSD) on top of traditional rotational hard disks for performance enhancement due to the significant IO improvements in SSD technology. It is widely recognized that automated data migration between SSD and HDD plays a critical role in effective integration of SSD into multi-tiered storage systems. Furthermore, effective data migration has to take into account of application specific workload characteristics, deadlines, and IO profiles. An important and interesting challenge for automated data migration in multi-tiered storage systems is how to fully release the power of data migration while guaranteeing the migration deadline is critical to maximizing the performance of SSD-enabled multi-tiered storage system. In this paper, we present an adaptive look ahead data migration model that can incorporate application specific characteristics and I/O profiles as well as workload deadlines. Our adaptive data migration model has three unique features. First, it incorporates a set of key factors that may impact on the performance of look ahead migration efficiency in our formal model develop. Second, our data migration model can adaptively determine the optimal look ahead window size, based on several parameters, to optimize the effectiveness of look ahead migration. Third, we formally and experimentally show that the adaptive data migration model can improve overall system performance and resource utilization while meeting workload deadlines. Through our trace driven experimental study, we compare the adaptive look ahead migration approach with the basic migration model and show that the adaptive migration model is effective and efficient for continuously improving and tuning of the performance and scalability of multi-tier storage systems.

High performance and energy-efficient storage systems are essential for mobile data-intensive applications such as remote surgery and mobile data center. Existing mobile storage systems consist of an array of independent small form factor hard disks connected to a host by a storage interface in a mobile computing environment. Although hard disks are cost-effective and can provide huge capacity and high-throughput, they have some intrinsic limitations such as long access latencies, high annual disk replacement rates, fragile physical characteristics, and energy-inefficiency. Compared with hard disk drives, solid state disks (SSD) are much more energy-efficient, and can offer much faster access times. A major concern on current solid state disk is its relatively higher price. In this paper, we developed hybrid mobile disk architecture HyBuM that integrates an array of solid state disks with buffer disks and an array of mobile disks. The most recently used data will be cached in the solid state disks, the second most popular data will be stored in the buffer disks, and the least used data sets will be stored in the mobile disk array. Experimental results demonstratively show that HyBuM provides significant energy saving for mobile storage systems such as laptops, mobile phones, and PDA compared to two existing non hybrid architecture.

Applications require storage systems to provide more and more storage space, at the same time; the performance of storage systems is also more and more demanding. In order to solve the contradiction between the cost and performance of storage system, hierarchical storage system composed of solid state disk and mechanical hard disk is widely used, which aims to obtain the performance of close solid state disk at the cost of approaching mechanical hard disk. Aiming at the problem of space utilization efficiency of solid-state disk, an adaptive hierarchical storage system is proposed ATS, ATS which can dynamically adjust the migration threshold according to the current access data scale of the load and the utilization of the storage device. The load can make full use of the storage space of solid-state disk without frequent data exchange at different levels. The experimental results show that compared with the static threshold mode and the MOD (Migrate on demand, access is migration) mode, ATS can obtain a better average response time regardless of whether the current load is in a case of a very large amount of data or a very small amount of data. ATS can reduce the average response time by up to 53% compared with the static threshold mode, and ATS can reduce the average response time by up to 50% compared with the MOD mode.

Solid State Disks (SSDs) are becoming increasingly popular due to enhancement in speed and reduction in size, power and cost. It is an obvious choice for many applications including personal computers, embedded systems, medical and healthcare devices etc. However, the reliability of SSD has now become a critical issue and this is an area of active research. SSD uses Flash technology which is a fast, efficient nonvolatile storage chip and offers cost-effective solution for SSDs. However, with all these features, flash memory defines a limit of write-erase on its blocks. Wearleveling policies extend SSD life time by ensuring even wearleveling of the blocks in a flash memory. Several algorithms have been proposed to improve wearleveling of SSD including Hot-Cold Swapping, Dual pool Algorithm (DP), Kim and Lee algorithm (KL) and Cost Age and Times Algorithm (CAT). This paper discusses all these wearleveling policies and introduces a Block Aging Prevention (BAP) technique which has been tested on 8Gb Flash. The comparison of all these algorithms show that the proposed technique has reduced the erasure count deviation of NAND flash blocks by 6.71% and 20% compared to DP and CAT respectively. It has also reduced overhead by 4% comparatively to DP.

Various key-value (KV) stores are widely employed for data management to support Internet services as they offer higher efficiency, scalability, and availability than relational database systems. The log-structured merge tree (LSM-tree) based KV stores have attracted growing attention because they can eliminate random writes and maintain acceptable read performance. Recently, as the price per unit capacity of NAND flash decreases, solid state disks (SSDs) have been extensively adopted in enterprise-scale data centers to provide high I/O bandwidth and low access latency. However, it is inefficient to naively combine LSM-tree-based KV stores with SSDs, as the high parallelism enabled within the SSD cannot be fully exploited. Current LSM-tree-based KV stores are designed without assuming SSD's multi-channel architecture.To address this inadequacy, we propose LOCS, a system equipped with a customized SSD design, which exposes its internal flash channels to applications, to work with the LSM-tree-based KV store, specifically LevelDB in this work. We extend LevelDB to explicitly leverage the multiple channels of an SSD to exploit its abundant parallelism. In addition, we optimize scheduling and dispatching polices for concurrent I/O requests to further improve the efficiency of data access. Compared with the scenario where a stock LevelDB runs on a conventional SSD, the throughput of storage system can be improved by more than 4X after applying all proposed optimization techniques.

Flash-based solid state disks (SSDs) are an alternative form of storage device that promises to deliver higher performance than the traditional mechanically rotating hard drives. While SSDs have seen utilization in embedded, consumer, and server computer systems, there has been little understanding of its performance effects with scientific I/O workloads. This paper provides a trace driven performance evaluation of scientific I/O workloads on SSDs. We find that SSDs only provide modest performance gains over mechanical hard drives due to the write-intensive nature of many scientific workloads. Other workloads (like read-mostly web servers) would likely see much larger gains. Additionally, we observe that the concurrent I/O (when multiple parallel processes simultaneously access a single storage device) may significantly affect the SSD performance. However, such effects appear to be dependent on specific SSD implementation features and they are hard to predict in a general fashion. These results suggest that abundant cautions are needed when supporting high-performance scientific I/O workloads on Flash-based SSDs.

State-of-the-art applications, such as convolutional neural networks, demand specialized hardware accelerators that address performance and efficiency constraints. An efficient memory hierarchy is mandatory for such hardware systems. While the memory architectures of general-purpose processors (e.g., CPU or GPUs) are based on cache systems, dedicated accelerators have mostly adopted the DMA (Direct Memory Access) concept due to the application field of image processing. DMA features like 2D data transfers or data padding can optimize the memory accesses of image processing. However, DMA lacks the capability to exploit temporal and spatial data reuse, a feature common in cache systems, particularly when multiple DMAs operate in parallel. This article proposes a novel Direct Cached Memory Access (DCMA) architecture, combining both DMA and cache methodologies and their respective advantages. Optimized for image-based AI algorithms, the DCMA architecture facilitates enhanced memory access by integrating multiple, parallel DMA ports with caching capabilities. This design allows for efficient data reuse and parallel memory access. Optimal parameters for the DCMA are determined through a comprehensive design space exploration. The DCMA is evaluated on a state-of-the-art Xilinx UltraScale+ FPGA board coupled with a massive-parallel vertical vector co-processor, called V 2 PRO. The results show the mitigation of the vector processor’s memory bottleneck. By using the proposed DCMA, speedups of up to ×17 for the ResNet-50 CNN can be achieved.

In this paper, a partial parity cache and data cache management method is presented for reducing the parity updating cost of a solid-state disk (SSD) based redundant array of inexpensive disk (RAID) system, thereby which the input/output (I/O) performance of the RAID system can be improved. SSDs have many advantages compared to hard disk drives. However, it is not advisable to directly add SSDs into a RAID system because doing so will decrease the performance and the life-time of the SSDs. In the RAID-5 system, parity generation includes read and write operations to the SSDs. Whenever there is a new write request to the RAID, the related parity must be updated and written to the SSDs. Such frequent parity updates result in poor RAID performance and shortens the life-time of the SSDs. This paper combines the prior methods and the proposed efficient buffer management method with a data cache. The proposed method reduces the number of read and write operations for generating parities in the RAID system. Experimental results show that the I/O performance of the RAID-5 system can be improved by 76% by using the proposed method.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Solid state disks (SSDs) consisting of NAND flash memory are replacing conventional HDDs in mobile and server markets. The major reason for such a widespread replacement is the high performance and low power consumption enabled by an SSD. It especially gives better performance and power efficiency for random requests, because it does not require slow-moving and power-hungry mechanical operations, e.g., motor control. For the performance of sequential requests, multi-channel/way parallel architectures are adopted, and the speed of the host interface is increased. Even though an SSD has better power efficiency than an HDD, the SSD power consumption must be minimized due to the stringent power consumption constraints of mobile and server products. This chapter presents a case study of developing an SSD power model with an application to low power SSD design. The power model is based on real measurement data. For accurate modeling, one must take into account the internal parallelism as well as power states. The case study shows that the power model is useful in evaluating the designs of dynamic power management policy.

Parallel circle frameworks are equipped for satisfying quickly expanding requests for both substantial stockpiling limit and high I/O execution. Be that as it may, it is trying to fundamentally increment circle I/O transfer speed for information escalated workloads because of the unwavering quality and moment handling of information solicitations under element workload conditions and the ideal tradeoff between framework adaptability and information dependability in information serious frameworks. To build the figuring execution and diminish power utilization, we proposed a novel half and half construction modeling that comprises of heterogeneous registering gadgets that comprises of Graphics Processing Unit (GPU) and Digital Signal Processor (DSP), Hard Disk Drive (HDD) exhibit and Solid State Disk (SSD). The most as often as could reasonably be expected utilized information will be put away as a part of the Solid state circles making the hard plates drive in a rest mode, however much as would be prudent to decrease the vitality utilization. We directed broad analyses to quantitatively assess the execution of the proposed construction modeling. Exploratory results demonstrate that coordinating GPU and DSP with the HDD and the SSD altogether lessen the force utilization over utilizing the GPU just without scarifying the execution.

The goal of this research is to design a PRAM-based SSD (solid state disk) updating management scheme which uses PRAM for main logging area of previous hybrid SSDs. Specifically the proposed scheme can provide higher performance and longer lifetime than those of previous scheme. Simulation results show that overall write performance can be enhanced by around 380% on average and the lifetime of SSD can be increased by up to 6.5 times.

The memory wall (the gap between processing and storage speeds) remains a concern to computer systems designers. Caches have played a key role in hiding the performance gap by keeping recently accessed information in fast memories closer to the processor. Multi and many core systems are placing severe demands on caches, exacerbating the performance disparity between memory and processors. New memory technologies including 3D stacked DRAMs, solid state disks (SSDs) such as those built using flash technologies and phase change memories (PCM) may alleviate the problem: 3D DRAMs and SSDs present lower latencies than conventional, off-chip DRAMs and magnetic disk drives. However these technologies force us to rethink how address spaces should be organized into pages and how virtual addresses should be translated into physical pages. In this paper, we present some preliminary ideas in this connection, and evaluate these new organizations using SPEC CPU2006 benchmarks.