Towards high performance and energy efficient storage systems using hybrid heterogeneous computing devices

High performance and energy-efficient storage systems are essential for mobile data-intensive applications such as remote surgery and mobile data center. Existing mobile storage systems consist of an array of independent small form factor hard disks connected to a host by a storage interface in a mobile computing environment. Although hard disks are cost-effective and can provide huge capacity and high-throughput, they have some intrinsic limitations such as long access latencies, high annual disk replacement rates, fragile physical characteristics, and energy-inefficiency. Compared with hard disk drives, solid state disks (SSD) are much more energy-efficient, and can offer much faster access times. A major concern on current solid state disk is its relatively higher price. In this paper, we developed hybrid mobile disk architecture HyBuM that integrates an array of solid state disks with buffer disks and an array of mobile disks. The most recently used data will be cached in the solid state disks, the second most popular data will be stored in the buffer disks, and the least used data sets will be stored in the mobile disk array. Experimental results demonstratively show that HyBuM provides significant energy saving for mobile storage systems such as laptops, mobile phones, and PDA compared to two existing non hybrid architecture.

A large write amplification ratio degrades the program/erase cycles (P/Es) of NAND Flashes and reduces the endurance and performance of solid state disks (SSDs). The lack of a practical way to measure write amplification for SSDs motivates us to propose a novel measuring method called RB-Explorer at the SSD level rather than the NAND Flash level. The goal of RB-Explorer is two-fold: (1) to accurately measure the write amplification of SSDs to quantify SSD endurance and (2) to study the impacts of I/O techniques on write amplification of SSDs. RB-Explorer incorporates a Ready/Busy (R/B) signal of one of the NAND Flashes in an SSD in a proposed write amplification model for SSDs with four full-parallelism levels (i.e., the channel, chip, die, and plane levels). RB-Explorer takes two steps toward measuring write amplification. First, RB-Explorer quantifies the number of page programs using the low R/B signal level, the duration of which varies with the different operation (i.e., read, program, and erase) in NAND Flash. Second, RB-Explorer measures data volume written to NAND Flashes by considering parallelisms at four levels. Data volume written to a die in a NAND Flash is obtained as a product of the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> ${\rm N_{p}}$</tex><mathgraphic fileref="sun-ieq1-2308207.gif" graphicformat="GIF"/></formula> of programs and page size <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm P_{a}}$</tex> <mathgraphic fileref="sun-ieq2-2308207.gif" graphicformat="GIF"/></formula> . Given the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq3-2308207.gif" graphicformat="GIF"/></formula> of channels, the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{chip}}$</tex> <mathgraphic fileref="sun-ieq4-2308207.gif" graphicformat="GIF"/></formula> of chips per channel, and the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{die}}$</tex> <mathgraphic fileref="sun-ieq5-2308207.gif" graphicformat="GIF"/></formula> of dies per chip, one can obtain the data volume written to NAND Flashes as a product of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{p}}, {\rm P_{a}}, {\rm N_{die}}, {\rm N_{chip}}$</tex><mathgraphic fileref="sun-ieq6-2308207.gif" graphicformat="GIF"/></formula> , and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq7-2308207.gif" graphicformat="GIF"/></formula> . RB-Explorer is applied to analyzing write amplification ratios of SSDs to track SSD endurance. Furthermore, we implement a real-world SSD (i.e., SSD-v) and employ a fine-tuned SSD simulator (i.e., SSDsim) to validate the accuracy of RB-Explorer. Our experimental results show that RB-Explorer improves on the accuracy of SSDsim—the state-of-the-art SSD simulator—in most tested cases. We conduct a series of measurements using micro-benchmarks and I/O traces to demonstrate how RB-Explorer may be applied to investigate SSDs.

Solid State Disks (SSDs) are becoming increasingly popular due to enhancement in speed and reduction in size, power and cost. It is an obvious choice for many applications including personal computers, embedded systems, medical and healthcare devices etc. However, the reliability of SSD has now become a critical issue and this is an area of active research. SSD uses Flash technology which is a fast, efficient nonvolatile storage chip and offers cost-effective solution for SSDs. However, with all these features, flash memory defines a limit of write-erase on its blocks. Wearleveling policies extend SSD life time by ensuring even wearleveling of the blocks in a flash memory. Several algorithms have been proposed to improve wearleveling of SSD including Hot-Cold Swapping, Dual pool Algorithm (DP), Kim and Lee algorithm (KL) and Cost Age and Times Algorithm (CAT). This paper discusses all these wearleveling policies and introduces a Block Aging Prevention (BAP) technique which has been tested on 8Gb Flash. The comparison of all these algorithms show that the proposed technique has reduced the erasure count deviation of NAND flash blocks by 6.71% and 20% compared to DP and CAT respectively. It has also reduced overhead by 4% comparatively to DP.

The need for transparency of data for a variety of public access, as well as guarantee the legal basis of the disclosure made significantly Open Government should be implemented in Indonesia. To support the Open Government thing to consider is the stability of access by the user, while the stability of access is influenced by two main issues, namely the specification of hardware (servers) and network.To optimize the server, we conducted a study of the technique In Memory Computing which is one technology that is rapidly growing in the era of Big Data Processing are included in clumps of High Performance Computing. Such technology is needed in areas that require very high computational intensity, because it has the ability to overcome the bottleneck that occurs in the system, especially on the permanent storage media such as Hard Disk Drive (HDD) and Solid State Disk (SSD). In this scientific study, carried out the design of hardware that can be applied to minimize the bottleneck that occurs and maximize the use of In Memory Computing technology, including the design of the specification as a central processing server to the network design specification required, so that can be easily done escalation when needed.

Various key-value (KV) stores are widely employed for data management to support Internet services as they offer higher efficiency, scalability, and availability than relational database systems. The log-structured merge tree (LSM-tree) based KV stores have attracted growing attention because they can eliminate random writes and maintain acceptable read performance. Recently, as the price per unit capacity of NAND flash decreases, solid state disks (SSDs) have been extensively adopted in enterprise-scale data centers to provide high I/O bandwidth and low access latency. However, it is inefficient to naively combine LSM-tree-based KV stores with SSDs, as the high parallelism enabled within the SSD cannot be fully exploited. Current LSM-tree-based KV stores are designed without assuming SSD's multi-channel architecture.To address this inadequacy, we propose LOCS, a system equipped with a customized SSD design, which exposes its internal flash channels to applications, to work with the LSM-tree-based KV store, specifically LevelDB in this work. We extend LevelDB to explicitly leverage the multiple channels of an SSD to exploit its abundant parallelism. In addition, we optimize scheduling and dispatching polices for concurrent I/O requests to further improve the efficiency of data access. Compared with the scenario where a stock LevelDB runs on a conventional SSD, the throughput of storage system can be improved by more than 4X after applying all proposed optimization techniques.

Applications require storage systems to provide more and more storage space, at the same time; the performance of storage systems is also more and more demanding. In order to solve the contradiction between the cost and performance of storage system, hierarchical storage system composed of solid state disk and mechanical hard disk is widely used, which aims to obtain the performance of close solid state disk at the cost of approaching mechanical hard disk. Aiming at the problem of space utilization efficiency of solid-state disk, an adaptive hierarchical storage system is proposed ATS, ATS which can dynamically adjust the migration threshold according to the current access data scale of the load and the utilization of the storage device. The load can make full use of the storage space of solid-state disk without frequent data exchange at different levels. The experimental results show that compared with the static threshold mode and the MOD (Migrate on demand, access is migration) mode, ATS can obtain a better average response time regardless of whether the current load is in a case of a very large amount of data or a very small amount of data. ATS can reduce the average response time by up to 53% compared with the static threshold mode, and ATS can reduce the average response time by up to 50% compared with the MOD mode.

Flash-based solid state disks (SSDs) are an alternative form of storage device that promises to deliver higher performance than the traditional mechanically rotating hard drives. While SSDs have seen utilization in embedded, consumer, and server computer systems, there has been little understanding of its performance effects with scientific I/O workloads. This paper provides a trace driven performance evaluation of scientific I/O workloads on SSDs. We find that SSDs only provide modest performance gains over mechanical hard drives due to the write-intensive nature of many scientific workloads. Other workloads (like read-mostly web servers) would likely see much larger gains. Additionally, we observe that the concurrent I/O (when multiple parallel processes simultaneously access a single storage device) may significantly affect the SSD performance. However, such effects appear to be dependent on specific SSD implementation features and they are hard to predict in a general fashion. These results suggest that abundant cautions are needed when supporting high-performance scientific I/O workloads on Flash-based SSDs.

Multi-tiered storage systems today are integrating Solid State Disks (SSD) on top of traditional rotational hard disks for performance enhancement due to the significant IO improvements in SSD technology. It is widely recognized that automated data migration between SSD and HDD plays a critical role in effective integration of SSD into multi-tiered storage systems. Furthermore, effective data migration has to take into account of application specific workload characteristics, deadlines, and IO profiles. An important and interesting challenge for automated data migration in multi-tiered storage systems is how to fully release the power of data migration while guaranteeing the migration deadline is critical to maximizing the performance of SSD-enabled multi-tiered storage system. In this paper, we present an adaptive look ahead data migration model that can incorporate application specific characteristics and I/O profiles as well as workload deadlines. Our adaptive data migration model has three unique features. First, it incorporates a set of key factors that may impact on the performance of look ahead migration efficiency in our formal model develop. Second, our data migration model can adaptively determine the optimal look ahead window size, based on several parameters, to optimize the effectiveness of look ahead migration. Third, we formally and experimentally show that the adaptive data migration model can improve overall system performance and resource utilization while meeting workload deadlines. Through our trace driven experimental study, we compare the adaptive look ahead migration approach with the basic migration model and show that the adaptive migration model is effective and efficient for continuously improving and tuning of the performance and scalability of multi-tier storage systems.

The data transfer rate is the traditional criterion for evaluating the overall performance of a hard disk. In this paper, the data transmission performance of hard disk was characterized based on fractal theory. The traditional mechanical hard disks and solid state disks with different capacities and specifications were tested and the corresponding signal graph of data transfer was analysed for the calculation of fractal dimension D. The results indicate that the process of hard disk data transfer has fractal characteristics; the fractal dimension D increases with the increase of the average transfer rate and the rotating speed of mechanical hard disk. However, there seems no direct correspondence between the fractal dimension D and the capacity of the hard disk; the larger the floating range of data transmission, the greater value of fractal dimension D.

The small slop approximation (SSA) is an accurate method to calculate the electromagnetic (EM) scattering properties of rough surfaces. However, its computational complexity restricts its application to smaller domains and there is always the need for speedup in very large cases using pure central processing units (CPUs) hardware. With the development of graphics processing units (GPUs), more processors are dedicated to perform independent calculations. In addition, NVIDIA introduced a parallel computing platform, compute unified device architecture (CUDA), which provides researchers an easy way to use processors on GPU. To calculate EM scattering properties on GPU, we reformulate the SSA method with CUDA to take advantage of GPU threads. Because each thread executes synchronously and deals with a corresponding point data of rough surface, the CUDA-based SSA method calculates faster than the pure-CPU equivalent. To overcome memory limitations, the data of large rough surface are stored on hard disk. Moreover, a subsidiary thread is used to deal with the process of data transmission between the memory and the hard disk and reduce transmitting time further. The factors, block size, data transfers, and register, are also discussed in the optimization of the CUDA application. Test cases running on a NVIDIA GTX 460 GPU indicate that two orders of magnitude speedup, including file input and output, is obtained with our new formulation.

Many applications actually require high performance, fault tolerant mass memories, which can be implemented using solid state devices. The high cost of semiconductor memories is a fundamental obstacle to the use of semiconductor devices instead of mechanical ones in mass storage memories. The use of faulty memories connected with an ECC VLSI circuit is proposed to overcome these problems. The authors present both a general purpose architecture which can be used as a transparent replacement of a normal hard disk and the coding-decoding circuit which uses the Reed-Solomon code for coding and an original modified error trapping technique for decoding. Using this algorithm it is possible to reach the high transfer rate necessary for high performance solid state disks (SSDs) and the requirements of fault tolerance needed to use faulty memories. The proposed decoding technique, patented, has been used by Texas Instruments in an on-the-shelf SSD.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Solid state disks (SSDs) consisting of NAND flash memory are replacing conventional HDDs in mobile and server markets. The major reason for such a widespread replacement is the high performance and low power consumption enabled by an SSD. It especially gives better performance and power efficiency for random requests, because it does not require slow-moving and power-hungry mechanical operations, e.g., motor control. For the performance of sequential requests, multi-channel/way parallel architectures are adopted, and the speed of the host interface is increased. Even though an SSD has better power efficiency than an HDD, the SSD power consumption must be minimized due to the stringent power consumption constraints of mobile and server products. This chapter presents a case study of developing an SSD power model with an application to low power SSD design. The power model is based on real measurement data. For accurate modeling, one must take into account the internal parallelism as well as power states. The case study shows that the power model is useful in evaluating the designs of dynamic power management policy.

In this paper, we propose a fast and simple system emulator, called a system performance emulator (SPE), to evaluate long read operations. The SPE estimates how much system-wide performance is enhanced by using a faster solid state disk (SSD). By suspending a CPU for a certain time during direct memory access (DMA) transfer and subtracting this suspended time from the total DMA time, the SPE estimates the improvement in system performance expected from an enhanced SSD prior to its manufacture. We also examine the relation between storage performance and system performance using the SPE.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.